AD5531BRU Analog Devices Inc, AD5531BRU Datasheet - Page 5

• Manufacturer Part Number: AD5531BRU
• Description: IC DAC 14BIT SRL IN/VOUT 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5531BRU

• Rohs Status: RoHS non-compliant
• Settling Time: 20µs
• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 60mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP

AC PERFORMANCE CHARACTERISTICS
V
otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
STANDALONE TIMING CHARACTERISTICS
V
otherwise noted.
Table 4.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
MAX
1
2
3
4
5
6
7
8
9
10
11
12
Guaranteed by design, not subject to production test.
Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with t
90% of V
LDAC
DD
DD
SYNC
SCLK
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
SDIN
CLR
= 10.8 V to 16.5 V, V
= 10.8 V to 16.5 V, V
1
1
LDAC CAN BE TIED PERMANENTLY LOW, IF REQUIRED.
DD
) and timed from a voltage level of (V
1, 2
t
6
Limit at T
7
140
60
60
50
40
50
40
15
5
50
5
50
MSB
t
SS
SS
4
DB15
= −10.8 V to −16.5 V; GND = 0 V; R
= −10.8 V to −16.5 V; GND = 0 V; R
MIN
, T
DB14
MAX
IL
+ V
t
7
DB11
IH
)/2.
B Version
20
120
0.5
100
1.3
t
1
t
8
Figure 2. Timing Diagram for Standalone Mode
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Unit
μs typ
nV-s typ
nV/√Hz typ
V/μs typ
nV-s typ
Rev. B | Page 5 of 20
LSB
DB0
L
L
= 5 kΩ and C
= 5 kΩ and C
t
5
t
3
t
9
Description
SCLK frequency
SCLK cycle time
SCLK low time
SCLK high time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Min SYNC high time
Data setup time
Data hold time
SYNC high to LDAC low
LDAC pulse width
LDAC high to SYNC low
CLR pulse width
t
t
10
2
Test Conditions/Comments
Full-scale change to ±½ LSB. DAC latch contents alternately
loaded with all 0s and all 1s.
DAC latch alternately loaded with 0x0FFF and 0x1000. Not
dependent on load conditions.
Effect of input bus activity on DAC output under test.
All 1s loaded to DAC.
L
L
= 220 pF to GND. All specifications T
= 220 pF to GND. All specifications T
t
11
t
12
AD5530/AD5531
MIN
MIN
R
= t
to T
to T
F
= 5 ns (10% to
MAX
MAX
, unless
, unless