MT47H128M8CF-25E:H TR Micron Technology Inc, MT47H128M8CF-25E:H TR Datasheet - Page 110
MT47H128M8CF-25E:H TR
Manufacturer Part Number
MT47H128M8CF-25E:H TR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H128M8CF-25EH_TR.pdf
(134 pages)
Specifications of MT47H128M8CF-25E:H TR
Lead Free Status / Rohs Status
Compliant
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Figure 62: WRITE-to-PRECHARGE
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
Command
Address
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
DQS#
DQS#
DQS#
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Bank a,
WRITE
Col b
T0
Notes:
WL + t DQSS
WL - t DQSS
WL + t DQSS
NOP
1. Subsequent rising DQS signals must align to the clock within
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following
4. BL = 4, CL = 3, AL = 0; thus, WL = 2.
5.
6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
7. A10 is LOW with the WRITE command (auto precharge is disabled).
T1
DI b.
t
and WRITE commands may be to different banks, in which case
the PRECHARGE command could be applied earlier.
WR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T2
DI
b
DI
b
T2n
1
NOP
1
T3
110
1
T3n
T4
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
T5
NOP
Transitioning Data
t WR
© 2004 Micron Technology, Inc. All rights reserved.
t
T6
DQSS.
NOP
t
WR is not required and
(a or all)
T7
Bank,
PRE
Don’t Care
t RP
WRITE
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