MT47H128M8CF-25E:H TR Micron Technology Inc, MT47H128M8CF-25E:H TR Datasheet - Page 116

• Manufacturer Part Number: MT47H128M8CF-25E:H TR
• Manufacturer: Micron Technology Inc

Specifications of MT47H128M8CF-25E:H TR

• Lead Free Status / Rohs Status: Compliant

SELF REFRESH
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet
refresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet
prior to CKE going back to HIGH. Once CKE is HIGH (
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for
ments is used to apply NOP or DESELECT commands for 200 clock cycles before
applying any other command.
t
XSNR. A simple algorithm for meeting both refresh and DLL require-
116
t
CKE specifications at least 1 ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
t
CK specifications at least 1 ×
t
CKE [MIN] has been satisfied
© 2004 Micron Technology, Inc. All rights reserved.
t
CK after entering self
SELF REFRESH
t
CK