LMX1600EVAL National Semiconductor, LMX1600EVAL Datasheet - Page 8

• Manufacturer Part Number: LMX1600EVAL
• Manufacturer: National Semiconductor

Specifications of LMX1600EVAL

• Lead Free Status / Rohs Status: Not Compliant

www.national.com
2.0 Programming Description
2.2.2 MAIN_R REGISTER
If the Control Bits (CTL [1:0]) are 1 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which
sets the Main PLL 12-bit R counter divide ratio and various control functions. The divide ratio is programmed using the bits
MAIN_R_CNTR as shown in table 2.2.3. The divider ratio must be ≥ 2. The charge pump control word (CP_WORD[3:0] ) sets the
charge pump gain and the phase detector polarity as detailed in 2.4.
2.2.3 12-Bit Programmable Main and Auxiliary Reference Divider Ratio
(MAIN/AUX R Counter)
Note 7: Legal divide ratio: 2 to 4,095.
2.3 PROGRAMMABLE FEEDBACK (N) DIVIDERS
2.3.1 AUX_N Register
If the Control Bits ( CTL[1:0]) are 0 1 when LE transitions high, data is transferred from the 18-bit shift register into the AUX_N
register latch which sets the Aux PLL 16-bit programmable N counter value. The AUX_N counter is a 16-bit counter which is fully
programmable from 240 to 65,535 for 1.1 GHz option or from 56 to 32,767 for 500 MHz option. The AUX_N register consists of
the 4-bit swallow counter (AUX_A_CNTR), the 12-bit programmable counter (AUX_B_CNTR). Serial data format is shown below.
The divide ratio (AUX_N_CNTR [13:0]) must be ≥ 240 (1.1 GHz option) or ≥ 56 (500 MHz option) for a continuous divide range.
The Aux PLL N divide ratio is programmed using the bits AUX_A_CNTR, AUX_B_CNTR as shown in tables 2.3.2.
2.3.2 4-BIT Swallow Counter Divide Ratio (Aux A COUNTER)
Note 8: Swallow Counter Value: 0 to 15
MAIN_R
AUX_N
Swallow
Swallow
Count
Count
(A)
(A)
15
0
1
•
0
First Bit
First Bit
17
17
500 MHz option
Divide Ratio
1.1 GHz option
CP_WORD[3:0]
4,095
16
16
2
3
•
3
0
0
1
X
•
3
AUX_A_CNTR
AUX_A_CNTR
15
15
2
0
0
1
2
0
•
14
14
11
0
0
1
•
1
0
0
1
1
0
•
AUX_B_CNTR[11:0]
13
13
10
0
0
1
•
0
0
0
0
1
1
•
MAIN_R_CNTR/AUX_R_CNTR
12
12
9
0
0
1
•
(Continued)
SHIFT REGISTER BIT LOCATION
SHIFT REGISTER BIT LOCATION
11
11
8
0
0
1
•
10
10
7
0
0
1
•
8
MAIN_R_CNTR[11:0]
9
9
Note 9: Swallow Counter Value: 0 to 7
6
0
0
1
•
8
8
5
0
0
1
•
X = Don’t Care condition
7
7
4
0
0
1
•
Swallow
Count
6
6
(A)
3
0
0
1
1
7
•
•
AUX_A_CNTR[3:0]
5
5
2
0
0
1
•
4
4
X
X
3
1
1
1
1
•
•
AUX_A_CNTR
3
3
2
0
1
0
0
1
1
•
•
2
2
1
0
1
•
Last Bit
Last Bit
1
1
1
0
0
1
1
•
0
0
0
1