PEF2054NV21XK Lantiq, PEF2054NV21XK Datasheet - Page 82

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Lantiq

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

Semiconductor Group
4.2.6.8 Version Number Status Register (VNSR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 0x
The VNSR register bits do not generate interrupts and are not modified by reading
VNSR. The IR and VN3..0 bits are read only bits, the SWRX bit is a write only bit.
IR
VN3..0
bit 7
IR
Initialization Request; this bit is set to logical 1 after an inappropriate clocking
or after a power failure. It is reset to logical 0 after a control memory reset
command: OMDR:OMS1..0 = 00, MACR = 7X.
Version status Number; these bits display the EPIC-1 chip version as follows
VN3..0
0000
0000
H
0
0
0
82
VN3
Chip Versions
A1, A2, A3 (EPIC-1)
1.0 (EPIC-S)
read
read
Detailed Register Description
VN2
address: D
OMDR:RBS = 1
address: 3A
VN1
PEB 2055
PEF 2055
H
bit 0
H
VN0