EMC6D102-CZC-TR Standard Microsystems (SMSC), EMC6D102-CZC-TR Datasheet - Page 16

• Manufacturer Part Number: EMC6D102-CZC-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of EMC6D102-CZC-TR

• Operating Current: 3mA
• Operating Temperature Classification: Commercial
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Revision 0.4 (09-25-07)
4.6
4.7
4.8
4.9
4.10
FIELD:
Bits:
Slave Device Time-Out
Stretching the SCLK Signal
SMBus Timing
Bus Reset Sequence
SMBus Alert Response Address
START
The EMC6D102 supports the slave device timeout as per the SMBus Specification, v2.0.
According to SMBus specification, v2.0 devices in a transfer can abort the transfer in progress and
release the bus when any single clock low interval exceeds 25ms (T
detected this condition must reset their communication and be able to receive a new START condition
no later than 35ms (T
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically
The EMC6D102 supports stretching of the SCLK by other devices on the SMBus. The Hardware
Monitor Block does not stretch the SCLK.
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing
diagram shown in the section titled
The SMBus Slave Interface will reset and return to the idle state upon a START field followed
immediately by a STOP field.
The EMC6D102 device responds to the SMBus Alert Response Address, 0001 100, if the INTEN bit
(register 7Ch bit 2) is set and one or more status events bits are high. The interrupt signal (INT#),
which can be enabled on either the PWM2 or TACH3 pins, can be used as the SMBALERT#. See the
section describing the
Pin on page 23
The device can signal the host that it wants to talk by pulling the SMBALERT# low, if a status bit is
set in one of the interrupt status registers and properly enabled onto the INT# pin. The host processes
the interrupt and simultaneously accesses all SMBALERT# devices through a modified Receive Byte
operation with the Alert Response Address (ARA).
The EMC6D102 device, which pulled SMBALERT# low, will acknowledge the Alert Response Address
and respond with its device address. The 7-bit device address provided by the EMC6D102 device is
placed in the 7 most significant bits of the byte. The eighth bit can be a zero or one.
After acknowledging the slave address, the EMC6D102 device will disengage the SMBALERT# pull-
down by clearing the INT enable bit. If the condition that caused the interrupt remains, the Fan Control
device will reassert the SMBALERT# on the next monitoring cycle, provided the INT enable bit has
been set back to ‘1’ by software.
1
may reset its communications port after a start or stop condition.
Table 4.4 Modified SMBus Receive Byte Protocol Response to ARA
RESPONSE
ADDRESS
ALERT
for more details on interrupts.
7
TIMEOUT, MAX
Interrupt Status Registers on page 21
Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
RD
1
).
DATASHEET
Section 9.2, "SMBus Interface," on page
ACK
16
1
EMC6D102 SLAVE
ADDRESS
and the section describing the
8
TIMEOUT, MIN
80.
NACK
). Devices that have
1
SMSC EMC6D102
Datasheet
STOP
Interrupt
1