EMC6D102-CZC-TR Standard Microsystems (SMSC), EMC6D102-CZC-TR Datasheet - Page 72

• Manufacturer Part Number: EMC6D102-CZC-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of EMC6D102-CZC-TR

• Operating Current: 3mA
• Operating Temperature Classification: Commercial
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Revision 0.4 (09-25-07)
7.2.33
Register
Address
85h
86h
87h
88h
Read/
Write
R
R
R
R
which is used to enable thermal events to force the interrupt pin (INT#) low if interrupts are enabled
(see Bit[2] INTEN of the Special Function register at offset 7Ch).
This register contains the following bits:
Bit[0] TEMP. Group temperature enable bit.
0=Out-of-limit temperature readings do not affect the state of the INT# pin (default)
1=Enable out-of-limit temperature readings to make the INT# pin active low
Bit[1] Ambient Temperature Status Enable bit.
Bit[2] Remote Diode 1 Temperature Status Enable bit.
Bit[3] Remote Diode 2 Temperature Status Enable bit
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The individual thermal error event bits are defined as follows:
0=disable
1=enable.
See
Registers 85h-88h: A/D Converter LSbs Registers
There is a 10-bit Analog to Digital Converter (ADC) located in the hardware monitoring block that
converts the measured voltages into 10-bit reading values. Depending on the averaging scheme
enabled, the hardware monitor may take multiple readings and average them to create the values
stored in the reading registers (i.e., 16x averaging, 32x averaging, etc.) The 8 MSb’s of the reading
values are placed in the Reading Registers. When the upper 8-bits located in the reading registers
are read the 4 LSb’s are latched into their respective bits in the A/D Converter LSbs Register. This
give 12-bits of resolution with a minimum value of 1/16
-127.9375 ºC < Temp < 127.9375 ºC and Voltage Range: 0 < Voltage < 256.9375) . See the DC
Characteristics for the accuracy of the reading values.
The eight most significant bits of the 12-bit averaged readings are stored in Reading registers and
compared with Limit registers. The Interrupt Status Register bits are asserted if the corresponding
measured value(s) on the inputs violate their programmed limits.
Figure 5.1 Interrupt Control on page
A/D Converter LSbs Reg 1
A/D Converter LSbs Reg 2
A/D Converter LSbs Reg 3
A/D Converter LSbs Reg 4
Register
Name
Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
VCC.3
(MSb)
RD2.3
V12.3
V50.3
Bit 7
DATASHEET
VCC.2
RD2.2
V12.2
V50.2
Bit 6
22.
72
VCC.1
RD2.1
V12.1
V50.1
Bit 5
th
RD2.0
VCC.0
V12.0
V50.0
Bit 4
per unit measured. (i.e., Temperature Range:
RD1.3
VCP.3
V25.3
AM.3
Bit 3
RD1.2
VCP.2
V25.2
AM.2
Bit 2
RD1.1
VCP.1
V25.1
AM.1
Bit 1
SMSC EMC6D102
RD1.0
VCP.0
(LSb)
V25.0
AM.0
Bit 0
Datasheet
Default
Value
N/A
N/A
N/A
N/A