LQ035Q7DH06/ES Sharp Electronics, LQ035Q7DH06/ES Datasheet - Page 11

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LQ035Q7DH06/ES

Manufacturer Part Number
LQ035Q7DH06/ES
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LQ035Q7DH06/ES

Lead Free Status / Rohs Status
Supplier Unconfirmed
7-2) Timing Characteristics of input signals
Table 7 AC Characteristics (1)
Parameter
Clock frequency of source driver
Set up time of data
Hold time of data
Vcom
【Note 7-7】There must be only one up-edge of DCLK (includes Tsusp and Thsp time) in the period of
driver
Source
driver
Gate
Clock frequency
Pulse width of clock(Low)
Pulse width of clock(High)
Rising time of clock
Falling time of clock
Setup time of clock
Hold time of clock
Frequency of start pulse
Setup time of start pulse
Hold time of start pulse
Rising time of start pulse
Falling time of start pulse
Setup time of Vcom
Hold time of Vcom
Rising time of clock
Falling time of clock
Pulse width (High level)
Pulse width (Low level)
Frequency of start pulse
Setup time of start pulse
Hold time of start pulse
Pulse width of start pulse
Setup time of latch pulse
Hold time of latch pulse
Pulse width of latch pulse
Setup time of PS
Setup time of PS
Hold time of PS
Hold time of PS
SPL=”Hi”.
Tsuvcom
Thvcom
Symbol
Twhcls
Tsusps
Tsulps
Twlcls
Tsucls
Tsusp
Tsups
Thsps
Thlps
Tsulp
Thcls
Trsps
Tfsps
Tcwh
Twsp
Thsp
Twlp
Thps
Tsud
Trcls
Thlp
Tfcls
Tcwl
fCK
Thd
fsps
Tcr
fcls
Tcf
fsp
Min.
16.5
16.5
100
300
4.5
10
20
20
60
30
15
10
58
40
40
15
30
0
1
0
5
0
0
1
3
Typ.
(1/fcls)-30
(VSHA=+5V, VSHD=+3.3V, Ta=25℃)
1.5/f
Max.
100
100
100
100
6.8
20
20
28
28
86
CK
MHz
Unit
kHz
kHz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
ns
ns
ns
μs
μs
ns
ns
μs
μs
ns
ns
ns
ns
μs
μs
DCLK
SPL,SPR
【Note 7-7】
LP
PS
R0~R5,G0~G5
,B0~B5
CLS
SPS
Vcom
LD-21909A-8
Remark

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