NS7520B-1-I55 Digi International, NS7520B-1-I55 Datasheet - Page 6
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NS7520B-1-I55
Manufacturer Part Number
NS7520B-1-I55
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Specifications of NS7520B-1-I55
Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NS7520B-1-I55
Manufacturer:
VBYONE
Quantity:
880
Company:
Part Number:
NS7520B-1-I55
Manufacturer:
Digi International
Quantity:
10 000
This table lists the key features of the NS7520.
2
Key Features
K e y F e a t u r e s
CPU core
13-Channel DMA controller
General purpose I/O pins
Three channels available for memory-to-memory
and receive
transmit and receive
Four channels for external peripherals. Only two
channels — either 3 and 5 or 4 and 6 — can be
configured at one time.
transfers
interrupt
ARM7TDMI 32-bit RISC processor
32-bit internal bus
32-bit ARM and 16-bit Thumb mode
15 general purpose 32-bit registers
32-bit program counter (PC) and status register
Five supervisor modes, one user mode
Two channels dedicated to Ethernet transmit
Four channels dedicated to two serial modules’
Flexible buffer management
16 programmable GPIO interface pins
4 pins programmable with level-sensitive
N S 7 5 2 0 D a t a s h e e t
0 3 / 2 0 0 6
Integrated 10/100 Ethernet MAC
Programmable Timers
Operating frequency
detection
18.432 MHz crystal
or crystal oscillator, or clock signal
operating frequencies from 10 to f
clock or using PLL multiplication f
10/100 Mbps MII-based PHY interface
10 Mbps ENDEC interface
TP-PMD and fiber-PMD device support
Full-duplex and half-duplex modes
Optional 4B/5B coding
Station, broadcast, and multicast address
512-byte transmit FIFO, 2 Kbyte receive FIFO
Intelligent receive-side buffer selection
Two independent timers (2μs–20.7 hours)
Watchdog timer (interrupt or reset on expiration)
Programmable bus monitor or timer
36, 46, or 55 MHz internal clock operation from
f
System clock source by external quartz crystal
Programmable PLL, which allows a range of
Maximum operating frequency from external
MAX
= 36, 46, or 55 (grade–dependent)
MAX
MAX