ADV7330KST Analog Devices Inc, ADV7330KST Datasheet
ADV7330KST
Specifications of ADV7330KST
Available stocks
Related parts for ADV7330KST
ADV7330KST Summary of contents
Page 1
FEATURES High Definition Input Formats 8-Bit or 16-Bit (4:2:2) Parallel YCrCb Compliant with: SMPTE 293M (525p) BTA T-1004 EDTV2 525p ITU-R BT.1358 (525p/625p) ITU-R BT.1362 (525p/625p) SMPTE 274M (1080i and 25 Hz SMPTE 296M (720p) Other High ...
Page 2
ADV7330 DETAILED FEATURES High Definition Programmable Features (720p/1080i) 2 Oversampling (148.5 MHz) Internal Test Pattern Generator (Color Hatch, Black Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control CGMS-A (720p/1080i) ...
Page 3
TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
ADV7330–SPECIFICATIONS Parameter 1 STATIC PERFORMANCE (With No Oversampling Ratio) Resolution Integral Nonlinearity 2 Differential Nonlinearity , +ve 2 Differential Nonlinearity , –ve DIGITAL OUTPUTS Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance ...
Page 5
DYNAMIC SPECIFICATIONS Parameter PROGRESSIVE SCAN MODE Luma Bandwidth Chroma Bandwidth SNR HDTV MODE Luma Bandwidth Chroma Bandwidth STANDARD DEFINITION MODE Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermodulation Chroma/Luma Gain Inequality Chroma/Luma Delay Inequality Luminance ...
Page 6
ADV7330 (V TIMING SPECIFICATIONS R Parameter 1 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK ...
Page 7
CLKIN HSYNC_I/P CONTROL VSYNC_I/P INPUTS BLANK_I/P Y7–Y0 C7–C0 HSYNC_O/P CONTROL VSYNC_O/P OUTPUTS BLANK_O CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 1. HD/PS ...
Page 8
ADV7330 CLKIN Y7–Y0 HSYNC_O/P CONTROL VSYNC_O/P OUTPUTS BLANK_O CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 3. PS 4:2:2 1 × 8-Bit Interleaved ...
Page 9
CLKIN HSYNC_I/P CONTROL VSYNC_I/P INPUTS BLANK_I/P Y7–Y0 HSYNC_O/P CONTROL VSYNC_O/P OUTPUTS BLANK_O/P CLKIN t 9 HSYNC_I/P CONTROL VSYNC_I/P INPUTS BLANK_I/P Y7–Y0 C7–C0 HSYNC_O/P CONTROL VSYNC_O/P OUTPUTS BLANK_O/P Figure 7. 16-Bit SD Pixel Input Mode (Input Mode 000) HSYNC_I/P VSYNC_I/P BLANK_I/P ...
Page 10
ADV7330 HSYNC_I/P VSYNC_I/P BLANK_I/P Y7– CLK CYCLES FOR 525p CLK CYCLES FOR 626p AS RECOMMENDED BY STANDARD Figure 9. PS 4:2:2, 1 × 8-Bit Interleaved Input Timing Diagram HSYNC_I/P VSYNC_I/P PAL = 24 CLK ...
Page 11
... Analog output short circuit to any power supply or common can indefinite duration. Model Temperature Range ADV7330KST 0°C to 70°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7330 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
Page 12
ADV7330 V Pin Number Mnemonic 11, 57 DGND 2, 3, 14, 15, TEST0–TEST14 51–55, 58–63 40 AGND 32 CLKIN 36 COMP 39 DAC A 38 DAC B 37 DAC C BLANK_I/P 25 HSYNC_I/P 23 VSYNC_I/P 24 4–9, 12, 13 Y7–Y0 ...
Page 13
Pin Number Mnemonic 10 45, 47 TEST15, TEST16 O 34 EXT_LF 31 RTC_SCR_TR BLANK_O/P 48 HSYNC_O/P 50 VSYNC_O GND_IO 42– REF TERMINOLOGY SD Standard definition ...
Page 14
ADV7330 Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a ...
Page 15
SR7– Register Bit Description SR0 00h Power Mode Sleep Mode. With this control enabled, the current consumption is reduced to µA level. All DACs and the internal PLL cct are disabled. I registers can be read from and written to ...
Page 16
ADV7330 SR7– Register Bit Description SR0 02h Mode Register 0 Reserved Test Pattern Black Bar RGB Matrix Sync on RGB RGB/YUV Output SD Sync HD Sync 03h RGB Matrix 0 04h RGB Matrix 1 05h RGB Matrix 2 06h RGB ...
Page 17
SR7– Register Bit Description SR0 10h HD Mode HD Output Standard Register 1 HD Input Control Signals HD 625p HD 720p HD BLANK Polarity HD Macrovision for 525p/625p 11h HD Mode HD Pixel Data Valid Register 2 HD Test Pattern ...
Page 18
ADV7330 SR7– Register Bit Description SR0 12h HD Mode Register Delay with respect to falling edge of HSYNC HD Color Delay with respect to falling edge of HSYNC HD CGMS HD CGMS CRC 13h HD Mode Register ...
Page 19
SR7– Register Bit Description SR0 1 16h HD Y Level 1 17h HD Cr Level 1 18h HD Cb Level 19h Reserved 1Ah Reserved 1Bh Reserved 1Ch Reserved 1Dh Reserved 1Eh Reserved Reserved 1Fh 20h HD Sharpness Filter HD Sharpness ...
Page 20
ADV7330 SR7- Register Bit Description SR0 38h HD Adaptive Filter HD Adaptive Filter Gain 1 Gain 1 Value A HD Adaptive Filter Gain 1 Value B 39h HD Adaptive Filter HD Adaptive Filter Gain 2 Gain 2 Value A HD ...
Page 21
SR7– Register Bit Description SR0 3Eh Reserved 3Fh Reserved 40h SD Mode Register 0 SD Standard SD Luma Filter SD Chroma Filter 41h Reserved 42h SD Mode Register 1 SD PrPb SSAF SD DAC Output 1 SD DAC Output 2 ...
Page 22
ADV7330 SR7– Register Bit Description SR0 44h SD Mode Register 3 SD VSYNC-3H SD RTC/TR/SCR* SD Active Video Length SD Chroma SD Burst SD Color Bars SD DAC Swap 45h Reserved 46h Reserved 47h SD Mode Register 4 SD PrPb ...
Page 23
SR7– Register Bit Description SR0 4Ah SD Timing Register 0 SD Slave/Master Mode SD Timing Mode SD BLANK Input SD Luma Delay SD Min. Luma Value SD Timing Reset SD HSYNC Width 4Bh SD Timing Register 1 SD HSYNC to ...
Page 24
ADV7330 SR7– Register Bit Description SR0 59h SD CGMS/WSS 0 SD CGMS Data SD CGMS CRC SD CGMS on Odd Fields SD CGMS on Even Fields SD WSS 5Ah SD CGMS/WSS 1 SD CGMS/WSS Data 5Bh SD CGMS/WSS 2 SD ...
Page 25
SR7– Register Bit Description SR0 65h SD DNR 2 DNR Input Select DNR Mode DNR Block Offset 66h SD Gamma A SD Gamma Curve A Data Points 67h SD Gamma A SD Gamma Curve A Data Points 68h SD Gamma ...
Page 26
ADV7330 SR7– Register Bit Description SR0 7Dh Reserved 7Eh Reserved 7Fh Reserved Macrovision 80h MV Control Bits Macrovision 81h MV Control Bits 82h Macrovision MV Control Bits 83h Macrovision MV Control Bits 84h Macrovision MV Control Bits Macrovision 85h MV ...
Page 27
INPUT CONFIGURATION Note that the ADV7330 defaults to progressive scan 54 MHz mode on power-up. Address(01h): Input Mode = 011 Standard Definition Address(01h): Input Mode = 000 The 8-bit multiplexed input data is input on Pins Y7–Y0, with Y0 being ...
Page 28
ADV7330 Table I provides an overview of possible input configurations. Input Format Total Bits ITU-R 8 BT.656 (27 MHz clock) 8 (54 MHz clock) 16 HDTV 16 OUTPUT CONFIGURATION Tables II and III show which output signals ...
Page 29
TIMING MODES HD Async Timing Mode [Subaddress 10h, Bit 3,2] For any input data that does not conform to the standards select- able in input mode, Subaddress 10h, asynchronous timing mode can be used to interface to the ADV7330. Timing ...
Page 30
ADV7330 HSYNC_I/P VSYNC_I/P BLANK_I/P* 1 → → → → → *When ...
Page 31
SD Real-Time Control, Subcarrier Reset, Timing Reset [Subaddress 44h, Bit 2,1] Together with the RTC_SCR_TR pin and SD Mode Register 3 [Address 44h, Bit 1,2], the ADV7330 can be used in timing reset mode, subcarrier phase reset mode, or RTC ...
Page 32
ADV7330 Reset Sequence A reset is activated with a high-to-low transition on the RESET pin (Pin 33) according to the Timing Specifications. The ADV7330 will revert to the default output configuration. Figure 24 illustrates the RESET sequence timing. SD VCR ...
Page 33
Vertical Blanking Interval The ADV7330 accepts input data that contains VBI data (such as CGMS, WSS, VITS and HD modes. For SMPTE 293M (525p) standards, VBI data can be inserted on Lines each frame, ...
Page 34
ADV7330 FILTER SECTION Table V shows an overview of the programmable filters available on the ADV7330. Table V. Selectable Filters of the ADV7330 Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL ...
Page 35
SD Internal Filter Response [Subaddress 40h; Subaddress 42, Bit 0] The Y filter supports several different frequency responses includ- ing two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost/attenuation, a CIF response, and a ...
Page 36
ADV7330–Typical Performance Characteristics PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) TPC 1. PS—UV (8 × Oversampling Filter (Linear)) PROG ...
Page 37
FREQUENCY (MHz) TPC 7. Luma NTSC Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 8. Luma PAL Low-Pass Filter ...
Page 38
ADV7330 –2 –4 –6 –8 –10 – FREQUENCY (MHz) TPC 13. Luma SSAF Filter—Programmable Responses – FREQUENCY (MHz) TPC 14. Luma ...
Page 39
FREQUENCY (MHz) TPC 19. Chroma 2.0 MHz LP Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 20. Chroma 1.3 MHz ...
Page 40
ADV7330 COLOR CONTROLS AND RGB MATRIX HD Y Level, Cr Level, Cb Level [Subaddress 16h–18h] Three 8-bit wide registers at Addresses 16h, 17h, 18h are used to program the output color of the internal HD test pattern genera- tor, whether ...
Page 41
SD Hue Adjust Value [Subaddress 60h] The hue adjust value is used to adjust the hue on the composite and chroma outputs. These eight bits represent the value required to vary the hue of the video data, i.e., the variance ...
Page 42
ADV7330 PROGRAMMABLE DAC GAIN CONTROL DACs A, B, and C are controlled by Reg 0B. The I registers will adjust the output signal gain up or down from its absolute level. CASE A GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, ...
Page 43
Gamma Correction [Subaddress 24h–37h for HD, Subaddress 66h–79h for SD] Gamma correction is available for SD and HD video. For each standard there are 20 8-bit wide registers. They are used to program the gamma correction curves A and B. ...
Page 44
ADV7330 HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL [Subaddress 20h, 38h–3Dh] There are three filter modes available on the ADV7330: sharp- ness filter mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y ...
Page 45
HD Sharpness Filter and Adaptive Filter Application Examples HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in ...
Page 46
ADV7330 ADAPTIVE FILTER CONTROL APPLICATION Figures 36 and 37 show a typical signal to be processed by the adaptive filter control block. Figure 36. Input Signal to Adaptive Filter Control Figure 37. Output Signal After Adaptive Filter Control The following ...
Page 47
SD Digital Noise Reduction [Subaddress 63h, 64h, 65h] DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal [DNR input select]. The absolute value of the filter output ...
Page 48
ADV7330 Block Size Control [Address 64h, Bit 7] This bit is used to select the size of the data blocks to be processed. Setting the block size control function to a Logic 1 defines a 16 pixel × 16 pixel ...
Page 49
VOLTS IRE:FLT 0 VOLTS IRE:FLT 0.5 0 –2 REV. B 100 L135 – Figure 44. Address 42h, Bit 100 L135 – ...
Page 50
ADV7330 BOARD DESIGN AND LAYOUT CONSIDERATIONS DAC Termination and Layout Considerations The ADV7330 contains an on-board voltage reference. The V through a 0.1 µF capacitor pin is normally terminated when the internal V is used. Alternatively, the ...
Page 51
H DAC 3 OUTPUT 6.8pF 600 600 6.8pF 4 560 560 Figure 48. Example Output Filter for PS, 8 × Oversampling DAC OUTPUT 3 470nH 220nH 75 1 300 33pF 82pF 4 Figure 49. Example Output Filter for HDTV, ...
Page 52
ADV7330 Digital Signal Interconnect The digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, ...
Page 53
APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM HD CGMS Data Registers 2–0 [Subaddress 21h, 22h, 23h] HD CGMS is available in 525p mode only, conforming to ‘CGMS-A EIA-J CPR1204-1, Transfer Method of Video ID Information Using Vertical Blanking Interval (525p system), March ...
Page 54
ADV7330 +700mV 70% 10% 0mV –300mV 5 +100 IRE +70 IRE 0 IRE –40 IRE 11.2 s +700mV REF 70% 10% 0mV –300mV 4T 3.128 s 90ns +700mV REF 70% 10% 0mV –300mV 4T 4.15 s ...
Page 55
APPENDIX 2—SD WIDE SCREEN SIGNALING [Subaddress 59h, 5Ah, 5Bh] The ADV7330 supports wide screen signaling (WSS) conform- ing to the standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the ADV7330 is configured in ...
Page 56
ADV7330 APPENDIX 3—SD CLOSED CAPTIONING [Subaddress 51h–54h] The ADV7330 supports closed captioning conforming to the standard television synchronizing waveform for color transmis- sion. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields ...
Page 57
APPENDIX 4—TEST PATTERNS The ADV7330 can generate SD and HD test patterns CH2 200mV M 10.0 s 30.6000 s T Figure 59. NTSC Color Bars T 2 CH2 200mV M 10 30.6000 s Figure 60. PA0L ...
Page 58
ADV7330 T 2 CH2 200mV M 4 1.82872ms Figure 65. 525p Field Pattern T 2 CH2 200mV M 4 1.84176ms Figure 66. 625p Field Pattern T 2 CH2 EVEN Figure 67. 525p Black Bar (–35 mV, ...
Page 59
The following register settings are used to generate a SD NTSC CVBS output on DAC A: Register Subaddress Setting 00h 10h 40h 10h 42h 40h 44h 40h 4Ah 08h All other registers are set to normal/default. For PAL CVBS output ...
Page 60
ADV7330 APPENDIX 5—SD TIMING MODES [Subaddress 4Ah] Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 = The ADV7330 is controlled by the SAV (start active video) and EAV (end active video) time ...
Page 61
Mode 0 (CCIR-656)—Master Option (Timing Register 0 TR0 = The ADV7330 generates H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in ...
Page 62
ADV7330 ANALOG VIDEO Mode 1—Slave Option (Timing Register 0 TR0 = this mode, the ADV7330 accepts horizontal SYNC and odd/ even field signals. A transition of the field ...
Page 63
Mode 1—Master Option (Timing Register 0 TR0 = this mode, the ADV7330 can generate horizontal sync and odd/even field signals. A transition of the field output when HSYNC_O/P is low indicates ...
Page 64
ADV7330 Mode 2—Slave Option (Timing Register 0 TR0 = this mode, the ADV7330 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC_I/P and VSYNC_I/P inputs indicates the ...
Page 65
Mode 2—Master Option (Timing Register 0 TR0 = this mode, the ADV7330 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC_O/P and VSYNC_O/P outputs indicates the ...
Page 66
ADV7330 Mode 3—Master/Slave Option (Timing Register 0 TR0 = this mode, the ADV7330 accepts or generates horizontal sync and odd/even field signals. ...
Page 67
DISPLAY 622 623 624 HSYNC_I/P BLANK_I/P FIELD EVEN FIELD DISPLAY 309 310 311 HSYNC_I/P BLANK_I/P FIELD EVEN FIELD APPENDIX 6—HD TIMING FIELD 1 1124 1125 VSYNC_I/P HSYNC_I/P FIELD 2 561 562 VSYNC_I/P HSYNC_I/P REV. B VERTICAL BLANK 625 1 2 ...
Page 68
ADV7330 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb Output Levels EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 83. EIA 770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 ...
Page 69
RGB Output Levels 700mV 550mV 300mV 700mV 300mV 700mV 300mV Figure 87. HD RGB Output Levels 700mV 550mV 300mV 0mV 700mV 300mV 0mV 700mV 300mV 0mV Figure 88. HD RGB Output Levels—RGB Sync Enabled REV. B 300mV 550mV 300mV 550mV ...
Page 70
ADV7330 YPrPb Output Levels 280mV 220mV 160mV 60mV Figure 91. U Levels—NTSC 280mV 220mV 160mV 60mV Figure 92. U Levels—PAL 2000mV 1260mV 1000mV 140mV Figure 93. U Levels—NTSC 332mV 110mV 332mV 110mV 2150mV 900mV –70– 2150mV 2000mV 1260mV 1000mV 900mV ...
Page 71
VOLTS IRE:FLT 0 APL = 44.5% 525 LINE NTSC SLOW CLAMP TO 0.00V AT 6.77 s VOLTS IRE:FLT 0.4 0.2 0 –0.2 –0.4 0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC-SOURCE! 525 LINE NTSC NO FILTERING SLOW CLAMP TO ...
Page 72
ADV7330 VOLTS IRE:FLT 0.6 0.4 0.2 0 –0.2 10 NOISE REDUCTION: 15.05dB APL = 44.3% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00V AT 6.72 s VOLTS 0.6 0.4 0.2 0 –0.2 0 NOISE REDUCTION: 0.00dB APL = 39.1% ...
Page 73
APL NEEDS SYNC = SOURCE 625 LINE PAL, NO FILTERING SLOW CLAMP TO 0.00V AT 6.72 s VOLTS 0 APL NEEDS SYNC = SOURCE 625 LINE PAL, NO FILTERING SLOW CLAMP TO 0.00V AT ...
Page 74
ADV7330 APPENDIX 8—VIDEO STANDARDS SMPTE274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 2116 2156 *FVH = FVH AND PARITY BITS SAV/EAV: LINE 1–562 ...
Page 75
ACTIVE VIDEO 522 523 524 525 ACTIVE VIDEO 622 623 624 625 747 748 749 750 FIELD 1 1124 1125 FIELD 2 561 562 REV. B VERTICAL BLANK Figure 105. SMPTE 293M ...
Page 76
ADV7330 10 1. 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW Revision History Location 7/04—Data sheet changed from REV REV. B. Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . ...