CY7C4241-25AXCT Cypress Semiconductor Corp, CY7C4241-25AXCT Datasheet - Page 12

CY7C4241-25AXCT

Manufacturer Part Number
CY7C4241-25AXCT
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4241-25AXCT

Configuration
Dual
Density
32Kb
Access Time (max)
15ns
Word Size
9b
Organization
4Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
40MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / Rohs Status
Compliant
Document #: 38-06016 Rev. *C
Switching Waveforms
Full Flag Timing
Programmable Almost Empty Flag Timing
Notes:
22. t
23. PAE offset = n.
24. If a Read is performed on this rising edge of the Read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
(if applicable)
(if applicable)
WCLK and the rising RCLK is less than t
SKEW2
WEN2
WEN2
Q
D
WCLK
WEN1
REN1,
WCLK
REN1,
RCLK
WEN1
REN2
RCLK
0
0
REN2
PAE
–Q
–D
OE
FF
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
8
8
t
DATA IN OUTPUT REGISTER
t
LOW
SKEW1
CLKH
[15]
t
ENS
NO Write
(continued)
t
SKEW2
SKEW2
t
WFF
t
t
A
ENH
t
t
ENS
ENS
, then PAE may not change state until the next RCLK.
[22]
t
t
ENH
ENH
t
CLKL
NO Write
t
DS
t
PAE
Note
23
DATA Write
DATA Read
t
ENS
t
t
SKEW1
WFF
CY7C4421/4201/4211/4221
[15]
N + 1 WORDS
t
ENS
INFIFO
t
ENS
CY7C4231/4241/4251
NO Write
t
ENH
t
WFF
t
t
A
ENH
Note
24
NEXT DATA Read
Page 12 of 19
DATA Write
t
PAE
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