AD603-EB Analog Devices Inc, AD603-EB Datasheet - Page 12

• Manufacturer Part Number: AD603-EB
• Manufacturer: Analog Devices Inc

Specifications of AD603-EB

• Lead Free Status / Rohs Status: Not Compliant

AD603
THE GAIN CONTROL INTERFACE
The attenuation is controlled through a differential, high
impedance (50 MΩ) input, with a scaling factor that is laser-
trimmed to 40 dB per volt, that is, 25 mV/dB. An internal band
gap reference ensures stability of the scaling with respect to
supply and temperature variations.
When the differential input voltage V
slider is centered, providing an attenuation of 21.07 dB. For the
maximum bandwidth range, this results in an overall gain of
10 dB (= −21.07 dB + 31.07 dB). When the control input is
−500 mV, the gain is lowered by +20 dB (= 0.500 V × 40 dB/V)
to −10 dB; when set to +500 mV, the gain is increased by
+20 dB to +30 dB. When this interface is overdriven in either
direction, the gain approaches either −11.07 dB (= − 42.14 dB +
+31.07 dB) or 31.07 dB (= 0 + 31.07 dB), respectively. The only
constraint on the gain control voltage is that it be kept within
the common-mode range (−1.2 V to +2.0 V assuming +5 V
supplies) of the gain control interface.
The basic gain of the AD603 can therefore be calculated by
where V
Programming the Fixed-Gain Amplifier Using Pin Strapping
section), the gain becomes
and
The high impedance gain control input ensures minimal
loading when driving many amplifiers in multiple channel
or cascaded applications. The differential capability provides
flexibility in choosing the appropriate signal levels and
polarities for various control schemes.
Gain (dB) = 40 V
Gain (dB) = 40 V
Gain (dB) = 40 V
G
is in volts. When Pin 5 and Pin 7 are strapped (see the
COMM
*NOMINAL VALUES.
GPOS
GNEG
VPOS
VNEG
VINP
G
G
G
+10
+ 20 for 0 to +40 dB
+ 30 for +10 to +50 dB
8
6
1
2
3
4
0dB
V
R
REFERENCE
G
–6.02dB
SCALING
2R
G
= 0 V, the attenuator
INTERFACE
R
CONTROL
–12.04dB –18.06dB –24.08dB
GAIN-
2R
R-2R LADDER NETWORK
R
2R
Figure 29. Simplified Block Diagram
R
Rev. H | Page 12 of 24
2R
(1)
(2)
PRECISION PASSIVE
INPUT ATTENUATOR
R
–30.1dB
AD603
2R
R
–36.12dB –42.14dB
For example, if the gain is to be controlled by a DAC providing
a positive-only, ground-referenced output, the gain control low
(GNEG) pin should be biased to a fixed offset of 500 mV to set
the gain to −10 dB when gain control high (GPOS) is at zero,
and to 30 dB when at 1.00 V.
It is a simple matter to include a voltage divider to achieve other
scaling factors. When using an 8-bit DAC having an FS output
of 2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)
results in a gain-setting resolution of 0.2 dB/bit. The use of such
offsets is valuable when two AD603s are cascaded, when
various options exist for optimizing the signal-to-noise profile,
as is shown in the Sequential Mode (Optimal SNR) section,
PROGRAMMING THE FIXED-GAIN AMPLIFIER
USING PIN STRAPPING
Access to the feedback network is provided at Pin 5 (FDBK).
The user may program the gain of the output amplifier of the
AD603 using this pin, as shown in Figure 30, Figure 31, and
Figure 32. There are three modes: in the default mode, FDBK
is unconnected, providing the range +9 dB/+51 dB; when V
and FDBK are shorted, the gain is lowered to −11 dB/+31 dB;
and, when an external resistor is placed between V
FDBK, any intermediate gain can be achieved, for example,
−1 dB/+41 dB. Figure 33 shows the nominal maximum gain vs.
external resistor for this mode.
2R
VIN
R
R
Figure 30. −10 dB to +30 dB; 90 MHz Bandwidth
VC1
VC2
FIXED-GAIN
AMPLIFIER
1
2
3
4
GPOS
GNEG
VINP
COMM
AD603
6.44kΩ*
694Ω*
20Ω*
VPOS
VOUT
VNEG
FDBK
7
5
8
7
6
5
VOUT
FDBK
VPOS
VNEG
OUT
VOUT
and
OUT