AD603-EB Analog Devices Inc, AD603-EB Datasheet - Page 17

• Manufacturer Part Number: AD603-EB
• Manufacturer: Analog Devices Inc

Specifications of AD603-EB

• Lead Free Status / Rohs Status: Not Compliant

APPLICATIONS INFORMATION
A LOW NOISE AGC AMPLIFIER
Figure 47 shows the ease with which the AD603 can be
connected as an AGC amplifier. The circuit illustrates many of
the points previously discussed: it uses few parts, has linear-in-
dB gain, operates from a single supply, uses two cascaded amplifiers
in sequential gain mode for maximum SNR, and an external
resistor programs each gain of the amplifier. It also uses a
simple temperature-compensated detector.
The circuit operates from a single 10 V supply. Resistors R1, R2,
R3, and R4 bias the common pins of A1 and A2 at 5 V. The
common pin is a low impedance point and must have a low
impedance path to ground, provided here by the 100 μF tantalum
capacitors and the 0.1 μF ceramic capacitors.
The cascaded amplifiers operate in sequential gain. Here, the
offset voltage between Pin 2 (GNEG) of A1 and A2 is 1.05 V
(42.14 dB × 25 mV/dB), provided by a voltage divider consisting of
Resistors R5, R6, and R7. Using standard values, the offset is not
exact, but it is not critical for this application.
The gain of both A1 and A2 is programmed by Resistors R13
and R14, respectively, to be about 42 dB; therefore, the maximum
gain of the circuit is twice that, or 84 dB. The gain control range
can be shifted up by as much as 20 dB by appropriate choices of
R13 and R14.
100µF
C 3
J 1
2
1
2
RT PR OVI D ES A 5 0Ω IN PU T I MPED A N C E.
C 3 A N D C 5 A R E TA NTA LU M.
+
0.1µF
100Ω
R T
C 4
1
2.49kΩ
R 1
0.1µF
0.1µF
10V
C7
C1
R 2
2.49kΩ
5.49kΩ
3
4
R 5
AD603
10V
1
A1
6
5.5V
2
100µF
2.49kΩ
7
R1 3
C 5
2
+
0.1µF
Figure 47. A Low Noise AGC Amplifier
0.1µF
C 2
SEQUENTIAL GAIN
C 6
1V OFFSET FOR
2.49kΩ
1.05kΩ
Rev. H | Page 17 of 24
R 6
R 3
0.1µF
10V
C8
R 4
2.49kΩ
3
4
AD603
The circuit operates as follows:
• A1 and A2 are cascaded.
• Capacitor C1 and the 100 Ω of resistance at the input of A1
• C2 blocks the small dc offset voltage at the output of A1
A half-wave detector is used, based on Q1 and R8. The current
into capacitor, C
current of Q2 (biased to be 300 μA at 300 K, 27°C) and the
collector current of Q1, which increases with the amplitude
of the output signal.
The automatic gain control voltage, V
of this error current. For V
insensitive to short-term amplitude fluctuations in the output
signal, the rectified current in Q1 must, on average, exactly
balance the current in Q2. If the output of A2 is too small to
do this, V
conducts sufficiently.
Consider the case where R8 is zero and the output voltage V
is a square wave at, for example, 455 kHz, which is well above
the corner frequency of the control loop.
10V
1
A2
form a time constant of 10 μs.
(which might otherwise saturate A2 at its maximum gain)
and introduces a high-pass corner at about 16 kHz,
eliminating low frequency noise.
THIS CAPACITOR SETS
AGC TIME CONSTANT
6
6.5V
2
AGC
2.49kΩ
7
R1 4
increases, causing the gain to increase until Q1
3.48kΩ
R 7
AV
0.1µF
, is the difference between the collector
AGC LINE
C
AV
V
AGC
10V
AGC
2N3906
2N3904
1.54kΩ
(and thus the gain) to remain
806Ω
Q2
Q1
R 9
R 8
10V
AGC
, is the time integral
5V
R1 0
1.24kΩ
R11
3.83kΩ
R1 2
4.99kΩ
0.1µF
C10
C9
0.1µF
C11
0.1µF
AD603
J 2
OUT