SPC5123YVY400B Freescale Semiconductor, SPC5123YVY400B Datasheet - Page 32

• Manufacturer Part Number: SPC5123YVY400B
• Manufacturer: Freescale Semiconductor

Specifications of SPC5123YVY400B

• Lead Free Status / Rohs Status: Compliant

Electrical and Thermal Characteristics
3.3.5.1
Notes:
1. Measured with clock pin loaded with differential 100 ohm termination resistor.
2. Measured with all outputs except the clock loaded with 50 ohm termination resistor to VDD_MEM_IO/2.
3. All transitions measured at mid-supply (VDD_MEM_IO/2)
4. In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.
5. Window position is given for t
Figure 7
32
Clock cycle time, CL=x
MCK AC differential crosspoint
voltage
CK HIGH pulse width
CK LOW pulse width
Skew between MCK and DQS
transitions
Address and control output setup
time relative to MCK rising edge
Address and control output hold
time relative to MCK rising edge
DQ and DM output setup time
relative to DQS
DQ and DM output hold time relative
to DQS
DQS-DQ skew for DQS and
associated DQ inputs
DQS window start position related to
CAS read command
shows the DDR SDRAM write timing.
Parameter
DDR and DDR2 SDRAM AC Timing Specifications
Table 20. DDR and DDR2 (DDR2-400) SDRAM Timing Specifications
At recommended operating conditions with VDD_MEM_IO of ±5%
DQSEN
= 2.0 t
t
t
t
Symbol
t
DS1(base)
DH1(base)
OS(base)
OH(base)
t
V
t
t
DQSEN
DQSQ
MPC5121E/MPC5123 Data Sheet, Rev. 3
DQSS
IX-AC
t
t
t
CK
CH
CL
CK.
For other values of t
VDD_MEM_IO*0.5
- t
t
t
t
t
CK
CK
CK
CK
CK
−0.25
5000
- 0.1
0.47
0.47
/2 - 750
/2 - 750
/4 - 500
/4 - 500
TBD
Min
/4 - 600
DQSEN,
VDD_MEM_IO * 0.5
window position is shifted accordingly.
t
CK
+ 0.1
/4 - 600
TBD
Max
0.53
0.53
0.25
—
—
—
—
—
Unit
t
t
t
ps
ps
ps
ps
ps
ps
ps
CK
CK
CK
V
Freescale Semiconductor
1,2,3,4,5
Notes
1,3
1,3
2,3
2,3
2,3
2,3
2,3
1
3
SpecID
A5.10
A5.11
A5.1
A5.2
A5.3
A5.4
A5.5
A5.6
A5.7
A5.8
A5.9