SPC5123YVY400B Freescale Semiconductor, SPC5123YVY400B Datasheet - Page 34

• Manufacturer Part Number: SPC5123YVY400B
• Manufacturer: Freescale Semiconductor

Specifications of SPC5123YVY400B

• Lead Free Status / Rohs Status: Compliant

Electrical and Thermal Characteristics
3.3.6
The PCI interface on the MPC5121e/MPC5123 is designed to PCI Version 2.3 and supports 33 and 66 MHz PCI operations.
See the PCI Local Bus Specification; the component section specifies the electrical and timing parameters for PCI components
with the intent that components connect directly together whether on the planar or an expansion board, without any external
buffers or other glue logic. Parameters apply at the package pins, not at expansion board edge connectors.
The PCI_CLK is used as output clock, the MPC5121e/MPC5123 is a PCI host device only.
Figure 11
the clock specifications.
34
2
shows the clock waveform and required measurement points for 3.3 V signaling environments.
1
2
3
In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK
requirements vary depending upon whether the clock frequency is above 33 MHz.
Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met
across the minimum peak-to-peak portion of the clock waveform as shown in
The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system
jitter.
Sym
t
t
t
high
PCI
—
cyc
low
Output
PCI CLK
PCI CLK Cycle Time
PCI CLK Slew Rate
PCI CLK High Time
PCI CLK Low Time
Description
0.3Vcc
0.4Vcc
0.5Vcc
Z
MPC5121E/MPC5123 Data Sheet, Rev. 3
0
Table 21. PCI CLK Specifications
= 50 Ω
Figure 11. PCI CLK Waveform
Figure 10. DDR AC Test Load
1,3
2
0.6Vcc
t
high
Min
1.5
15
6
6
66 MHz
t
2
cyc
0.2Vcc
t
Max
1
R
low
30
—
—
4
L
= 50 Ω
Min
30
11
11
1
33 MHz
VDD_MEM_IO/2
0.4Vcc, p-to-p
(minimum)
Figure
Max
—
—
—
4
11.
Units SpecID
V/ns
Freescale Semiconductor
ns
ns
ns
Table 21
A6.1
A6.2
A6.3
A6.4
summarizes