ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet
ST7265XEVALMS
Specifications of ST7265XEVALMS
ST7265XEVALMS Summary of contents
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... A/D Converter (ADC) with 8 channels Instruction Set ■ – 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – unsigned multiply instruction – True bit manipulation Development Tools ■ – Full hardware/software development package ST72651 ST72F651 32K ROM 32K FLASH 5K (256) ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 154 15.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 155 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.1 SPI MULTIMASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARD- WARE WATCHDOG OPTION ...
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ST7265x 1 INTRODUCTION The ST7265x MCU supports volume data ex- change with a host (computer or kiosk) via a full speed USB interface. The MCU is capable of han- dling various transfer protocols, with a particular emphasis on mass storage ...
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INTRODUCTION (Cont’d) In addition to the peripherals for USB full speed data transfer, the ST7265x includes all the neces- sary features for stand-alone applications with FLASH mass storage. – Low voltage reset ensuring proper power-on or power-off of the device ...
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ST7265x INTRODUCTION (Cont’d) Figure 3. ST7265x Block Diagram OSCIN 12MHz OSCOUT 48MHz TRANSFER (1280 bytes) USBDP USBDM USBVCC PD[7:0] (8 bits) 16-BIT TIMER* RESET not available on all products (refer to Table 1: Device Summary) 6/163 1 ...
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PIN DESCRIPTION Figure 4. 48-Pin LQFP Package Pinout USBV USBDM USBVCC USBV DTC/PB0 DTC/PB1 DTC/PB2 DTC/PB3 DTC/PB4 USBDP ...
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ST7265x PIN DESCRIPTION (Cont’d) Figure 5. 64-Pin LQFP Package Pinout USBV SS USBDM USBDP USBVCC USBV DD V DDF V SSF DTC / PE5 (HS) DTC / PE6 (HS) DTC / PE7 (HS) DTC / PB0 DTC / PB1 DTC ...
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PIN DESCRIPTION (Cont’d) Legend / Abbreviations: Type input output supply V powered: I/O powered by the alternate sup- DDF ply rail, supplied by V and V DDF In/Output level CMOS 0.3V T ...
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ST7265x Pin Pin Name 12 15 PB4/DTC I PB5/DTC I PB6/DTC I PB7/DTC I PA0/DTC I PA1/DTC I PA2/DTC I PA3/DTC I PA4/DTC I/O ...
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Pin Pin Name 34 45 PE0/DTC/AIN4 I PE1/DTC/AIN5 I PE2/DTC/AIN6 I/O PE3/AIN7/DTC I/O PWM0 38 49 PE4/PWM1 I /ICCSEL RESET I PF0 / SCL I/O ...
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ST7265x Figure 6. Multimedia Card Or Secure Digital Card Writer Application Example 100nF 4.7µF USBV DD =4.0-5.5V USBVDD USB Port 1.5KΩ USB 5V VCC 100nF USB GND GND MultiMedia Card Pin ST72F65 pin (1) ST7 / ...
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Figure 7. Smartmedia Card Writer Or Flash Drive Application Example 100nF 4.7µF USBV DD =4.0-5.5V USBVDD USB Port 1.5KΩ USB 5V VCC 100nF USB GND GND level translator V DDF 100nF Table 2. SmartMedia Interface Pin ...
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ST7265x Figure 8. Compact Flash Card Writer Application Example 100nF 4.7µF USBV DD =4.0-5.5V USBVDD USB Port 1.5KΩ USB 5V VCC 100nF USB USB GND GND 1 level translator Table 3. Compact Flash Card Writer Pin ...
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Figure 9. Sony Memory Stick Writer Ap3plication Example 100nF 4.7µF USBV DD =4.0-5.5V USBVDD USB Port 1.5KΩ USB 5V VCC 100nF USB GND GND PC0 CD CLK BS DAT MultiMedia Card Pin ST72F65 pin (1) ST7 ...
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ST7265x 3 REGISTER & MEMORY MAP As shown in Figure 10, the MCU is capable of ad- dressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 80 bytes of register locations Kbytes ...
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Table 4. Hardware Register Memory Map Address Block Register Label 0000h PADR 0001h PADDR 0002h PAOR 0003h PBDR 0004h PBDDR 0005h 0006h PCDR 0007h PCDDR 0008h PCOR 0009h PDDR 000Ah PDDDR 000Bh PDOR 000Ch PEDR 000Dh PEDDR 000Eh PEOR 000Fh ...
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ST7265x Address Block Register Label 0020h TCR1 0021h TCR2 0022h TSR 0023h CHR 0024h CLR 0025h TIM ACHR 0026h ACLR 0027h OC1HR 0028h OC1LR 0029h OC2HR 002Ah OC2LR 002Bh Flash 002Ch ITSPR0 002Dh ITSPR1 ITC 002Eh ITSPR2 002Fh ITSPR3 0030h ...
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Address Block Register Label 004Ch MISCR3 004Dh PWM0 1) 004Eh PWM BRM10 004Fh PWM1 Note 1. If the peripheral is present on the device (see Device Summary on page 1) Register name Miscellaneous Register 3 10-bit PWM/BRM registers ST7265x Reset ...
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ST7265x 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ba- sis ...
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Figure 11. Memory Map and Sector Address 4K 8K 1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh 10K 16K 24K 32K 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 4 Kbytes 4 Kbytes ST7265x 48K 60K DV FLASH MEMORY ...
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... The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Program- ming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OS- ...
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... Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the spe- cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap- ...
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ST7265x 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 ...
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CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. ...
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ST7265x CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next ...
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SUPPLY, RESET AND CLOCK MANAGEMENT 6.1 CLOCK SYSTEM 6.1.1 General Description The MCU accepts either a 12 MHz crystal or an external clock signal to drive the internal oscillator. The internal clock ( derived from the inter- ...
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ST7265x 6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These sources act ...
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RESET SEQUENCE MANAGER (Cont’d) 6.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ac- cordance with the ...
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ST7265x RESET SEQUENCE MANAGER (Cont’d) In stand-alone mode, the 512 CPU clock cycle de- lay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. Figure 19. Reset Delay in Stand-alone Mode RESET DELAY ...
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LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below a V DDA value. This means ...
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ST7265x 6.4 POWER SUPPLY MANAGEMENT 6.4.1 Single Power Supply Management In applications operating only when connected to the USB (Flash writers, Backup systems), the mi- crocontroller must operate from a single power supply (i.e. USB bus power supply or the ...
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... USB SWITCH 4V min. from USB Note 1: Ground lines not shown Note 2: Suggested device: STN3PF06 (STMicroelectronics) Note 3: To allow USB cable unplug detection, output voltage of step-up converter should be low enough to not enduce (through PMOS substrate diode) voltage greater than USBV on USBV ...
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ST7265x POWER SUPPLY MANAGEMENT (Cont’d) 6.4.2.2 Switching from USB Mode to Stand- Alone Mode In USB Mode, when the user unplugs the USB ca- ble, the voltage level drops on the USBV The on-chip Power Supply Manager generates a PLG ...
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POWER SUPPLY MANAGEMENT (Cont’d) Figure 24. Power Supply Management: Dual Power Supply STAND-ALONE USBV SUPPLY SUPPLY VOLTAGES PLG INTERRUPT REQUEST RESET S/W STAND-ALONE RESET STATUS PROCESSING USBEN HI-Z V IT+(LVD) STAND-ALONE V pin DD voltage PLL PLL OFF ON/OFF 48 ...
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ST7265x POWER SUPPLY MANAGEMENT (Cont’d) 6.4.3 Storage Media Interface I/Os The microcontroller is able to drive Storage Media through an interface operating at a different volt- age from the rest of the circuit. This is achieved by powering the Storage ...
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POWER SUPPLY MANAGEMENT (Cont’d) 6.4.4 Register Description POWER CONTROL REGISTER (PCR) Reset Value: 0000 0000 (00h) 7 ITM PLG VSE ITPF PLG Bit 7 = ITPF Voltage Input Threshold Plus Flag This bit is set by hardware ...
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ST7265x 7 INTERRUPTS 7.1 INTRODUCTION The CPU enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt management: – software programmable nesting levels ...
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INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if ...
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ST7265x INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see ...
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INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft- ...
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ST7265x INTERRUPTS (Cont’d) Table 9. Dedicated Interrupt Instruction Set Instruction New Description HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1:0=11 JRNM Jump if I1:0<>11 POP CC Pop CC from the Stack RIM Enable interrupt (level 0 ...
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INTERRUPTS (Cont’d) Table 11. Nested Interrupts Register Map and Reset Values Address Register 7 Label (Hex.) 002Ch I1_3 ISPR0 Reset Value 1 002Dh I1_7 ISPR1 Reset Value 1 002Eh I1_11 ISPR2 1 Reset Value 002Fh ISPR3 Reset Value 1 6 ...
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ST7265x 8 POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, two main pow- er saving modes are implemented in the ST7. After a RESET the normal operating ...
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POWER SAVING MODES (Cont’d) 8.3 HALT MODE The HALT mode is the MCU lowest power con- sumption mode. The HALT mode is entered by ex- ecuting the HALT instruction. The internal oscilla- tor is then turned off, causing all internal ...
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ST7265x 9 I/O PORTS 9.1 INTRODUCTION Important note: Please note that the I/O port configurations of this device differ from those of the other ST7 devices. The I/O ports offer different functional modes: – transfer of data through digital inputs ...
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I/O PORTS (Cont’d) 9.2.2 Output Modes Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status: DR Push-pull The output ...
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ST7265x I/O PORTS (Cont’d) Figure 31. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL EXTERNAL INTERRUPT SOURCE ( POLARITY SELECTION Table 12. I/O Port ...
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I/O PORTS (Cont’d) Table 13. I/O Port Configurations NOT IMPLEMENTED TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD Notes: 1. When ...
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ST7265x I/O PORTS (Cont’d) 9.2.5 Bit manipulation on Open Drain Outputs As mentioned in Section 9.2.2, software should avoid using bit manipulation instructions on the DR register in open drain output mode, but must al- ways access it using byte ...
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I/O PORTS (Cont’d) 9.4 Register Description DATA REGISTER (DR) Port x Data Register PxDR with Read/Write Reset Value: 0000 0000 (00h Bits 7:0 = D[7:0] ...
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ST7265x I/O PORTS (Cont’d) Table 15. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) Reset Value of all I/O port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0003h PBDR MSB 0004h PBDDR 0005h 0006h PCDR ...
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MISCELLANEOUS REGISTERS MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS21 IS20 Bits 7:6 = IS1[1:0] ei0 Interrupt sensitivity Interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei0 interrupts (Port ...
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ST7265x MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Reset Value: 0000 0000 (00h Bits 7:5 = Reserved. Bits 4:0 = P[4:0] Power Management Bits These bits are set and cleared by software. They can ...
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ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...
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ST7265x WATCHDOG TIMER (Cont’d) 11.1.4 Software Watchdog Option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to ...
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WATCHDOG TIMER (Cont’d) 11.1.8 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by Table 18. Watchdog ...
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ST7265x 11.2 DATA TRANSFER COPROCESSOR (DTC) 11.2.1 Introduction The Data Transfer Coprocessor is a Universal Se- rial/Parallel Communications Interface. By means of software plug-ins provided by STMicroelectron- ics, the user can configure the ST7 to handle a wide range of ...
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... Loading the Protocol Software The DTC must first be initialized by loading the protocol-specific software plug-in (provided by STMicroelectronics) into the DTC RAM this: 1. Stop the DTC by clearing the RUN bit in the DTCCR register 2. Remove the write protection by setting the LOAD bit in the DTCCR register 3 ...
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ST7265x Data Transfer Coprocessor (Cont’d) 11.2.7 Interrupts Enable Event Interrupt Event Control Flag Bit Error ERROR ERREN Stop STOP STOPEN Note: The DTC interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if ...
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Data Transfer Coprocessor (Cont’d) Table 19. DTC Register Map and Reset Values Address Register Label (Hex.) 1C DTCCR 1D DTCSR MSB 1F DTCPR ERREN ...
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ST7265x 11.3 USB INTERFACE (USB) 11.3.1 Introduction The USB Interface implements a full-speed func- tion interface between the USB and the ST7 mi- crocontroller highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and USB ...
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USB INTERFACE (Cont’d) USB Endpoint RAM Buffers There are five bidirectional Endpoints including one control Endpoint 0. Endpoint 1 and Endpoint 2 are counted as 4 bulk or interrupt Endpoints (two IN and two OUT). Endpoint 0 and Endpoint 1 ...
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ST7265x USB INTERFACE (Cont’d) Figure 39. Endpoint 2 Upload Mode selected by MOD[1:0] Bits = 01b 1550h Endpoint 0 Buffer OUT Endpoint 0 Buffer IN Endpoint 1 Buffer OUT Endpoint 1 Buffer IN 158Fh Endpoint 2 Buffer OUT Endpoint 2 ...
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... USB Data Buffer Manager with the Data Transfer Coprocessor (DTC). These flags are used by the software plug-ins provided by STMicroelectronics) running on the DTC. 11.3.4.1 Data Transfer Modes In USB normal mode (MOD[1:0]=00b), the maxi- mum memory size of Endpoint bytes, and therefore reception of 512 bytes packets requires ST7 software intervention every 64 bytes ...
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ST7265x USB INTERFACE (Cont’d) Figure 40. Overview of USB, DTC and ST7 Interconnections BUFCSR Register (19h) BUF NUM 66/163 1 USB SIE STAT STAT CLR B1 B0 USB DATA BUFFER MANAGER BUFFER ACCESS ARBITRATION DATA TRANSFER ...
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USB INTERFACE (Cont’d) 11.3.5 Low Power modes Mode No effect on USB. WAIT USB interrupt events cause the device to exit from WAIT mode. USB registers are frozen. In halt mode, the USB is inactive. USB operations resume when the ...
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ST7265x USB INTERFACE (Cont’d) 11.3.7 Register Description BUFFER CONTROL/STATUS (BUFCSR) Read Only (except bit 0, read/write) Reset Value: 0000 0000 (00h) 7 BUF NUM Bits 7:4 = Reserved, forced by hardware to 0. Bit 3 = ...
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USB INTERFACE (Cont’d) Bit 4 = ERR Error. This bit is set by hardware whenever one of the er- rors listed below has occurred error detected 1: Timeout, CRC, bit stuffing, nonstandard framing or buffer overrun error detected ...
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ST7265x USB INTERFACE (Cont’d) Bit 2 = PDWN Power down. This bit is set by software to turn off the 3.3V on- chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage ...
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USB INTERFACE (Cont’d) Bits 2:0 = ERR[2:0] Error type. These bits identify the type of error which oc- curred: ERR2 ERR1 ERR0 Meaning error Bitstuffing error CRC error EOP error ...
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ST7265x USB INTERFACE (Cont’d) Bits 1:0 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the end- point status, as listed below: Table 21. Reception Status Encoding STAT_RX1 STAT_RX0 DISABLED: no function can be executed ...
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USB INTERFACE (Cont’d) ENDPOINT 1 TRANSMISSION (EP1TXR) Read/Write Reset value: 0000 0000 (00h) 7 CTR_T This register is used for controlling Endpoint 1 transmission. Bits 2:0 are also reset by a USB re- set, either ...
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ST7265x USB INTERFACE (Cont’d) Download Mode IN transactions are managed the same way as in normal mode (by software with the help of CTR in- terrupt) but OUT transactions are managed by hardware. This means that no CTR interrupt is ...
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USB INTERFACE (Cont’d) Bit 2= DTOG_TX Data Toggle, for transmission transfers. This bit contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. DTOG_TX and DTOG_RX are normally updated by hardware, on receipt of a ...
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ST7265x Table 26. USB Register Map and Reset values Address Register 7 Name (Hex.) BUFCSR 0 47 Reset Value 0 USBISTR CTR 30 Reset Value 0 USBIMR CTRM 31 Reset Value 0 USBCTLR RSM 32 Reset Value 0 DADDR 33 ...
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TIMER 11.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. 11.4.2 Main Features Programmable prescaler: f ■ CPU Overflow status flag and maskable interrupt ■ Output compare functions with ■ – 2 ...
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ST7265x 16-BIT TIMER (Cont’d) Figure 41. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT 0 OCF1 TOF 0 0 OCIE TOIE FOLV2 TIMER INTERRUPT 78/163 1 ST7 INTERNAL ...
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TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Read At t0 +∆t LS Byte Sequence completed The user must read the ...
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ST7265x 16-BIT TIMER (Cont’d) Figure 42. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 43. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET ...
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TIMER (Cont’d) 11.4.3.2 Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate ...
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ST7265x 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin ...
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TIMER (Cont’d) Figure 46. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) Figure 47. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER ...
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ST7265x 16-BIT TIMER (Cont’d) 11.4.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode ...
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TIMER (Cont’d) 11.4.6 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ...
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ST7265x 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (TCR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E 0 0 CC1 CC0 Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from ...
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TIMER (Cont’d) OUTPUT COMPARE 1 (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 1 (OC1LR) Read/Write ...
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ST7265x 16-BIT TIMER (Cont’d) Table 28. 16-Bit Timer Register Map and Reset Values Address Register 7 Name (Hex.) TCR1 20 Reset Value TCR2 OC1E 21 Reset Value TSR 22 Reset Value CHR MSB 23 Reset Value CLR MSB 24 Reset ...
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PWM/BRM GENERATOR (DAC) 11.5.1 Introduction This PWM/BRM peripheral includes a 6-bit Pulse Width Modulator (PWM) and a 4-bit Binary Rate Multiplier (BRM) Generator. It allows the digital to analog conversion (DAC) when used with external filtering. Note: The number ...
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ST7265x PWM/BRM GENERATOR (Cont’d) PWM/BRM Outputs The PWM/BRM outputs are assigned to dedicated pins. The PWM/BRM outputs can be connected filter (see Figure 49 for an example). The RC filter time must be higher than T Figure ...
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PWM/BRM GENERATOR (Cont’d) BRM Generation The BRM bits allow the addition of a pulse to wid standard PWM pulse for specific PWM cy- cles. This has the effect of “fine-tuning” the PWM Duty cycle (without modifying the base ...
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ST7265x PWM/BRM GENERATOR (Cont’d) Figure 52. Simplified Filtered Voltage Output Schematic with BRM Added VDD PWMOUT 0V VDD OUTPUT VOLTAGE 0V Figure 53. Graphical Representation of 4-Bit BRM Added Pulse Positions BRM VALUE 0001 bit0=1 0010 bit1=1 ...
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PWM/BRM GENERATOR (Cont’d) Figure 54. Precision for PWM/BRM Tuning for VOUTEFF (After filtering) 11.5.4 Register Description On a channel basis, the 10 bits are separated into two data registers: Note: The number of PWM and BRM channels available depends on ...
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ST7265x PULSE WIDTH MODULATION (Cont’d) Table 31. PWM Register Map and Reset Values Address Register 7 Name (Hex.) PWM0 1 4D Reset Value 1 BRM10 B7 4E Reset Value 0 PWM1 1 4F Reset Value 1 94/163 ...
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SERIAL PERIPHERAL INTERFACE (SPI) 11.6.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not ...
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ST7265x SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 56. The MOSI pins are connected together and the MISO pins are connected together. In ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM ...
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ST7265x SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 59). Note: The idle state of SCK must correspond to the polarity selected ...
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ST7265x SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.5 Error Flags 11.6.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.5.4 Single Master System A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 61). The master device selects the individual slave de- vices by ...
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ST7265x SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt ...
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ST7265x SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Table 33. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 19 Reset Value SPICR SPIE 1A Reset Value SPICSR SPIF 1B Reset Value SPE SPR2 MSTR ...
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ST7265x 11.7 I²C SINGLE MASTER BUS INTERFACE (I2C) 11.7.1 Introduction 2 The I C Bus Interface serves as an interface be- tween the microcontroller and the serial I provides single master functions, and controls all bus-specific sequencing, ...
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I²C SINGLE MASTER BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. 2 The speed of the I C interface may be selected between Standard (up to 100KHz) and Fast I (up to 400KHz). SDA/SCL Line Control Transmitter ...
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ST7265x I²C SINGLE MASTER BUS INTERFACE (Cont’d) 11.7.4 Functional Description (Master Mode) Refer to the CR, SR1 and SR2 registers in 11.7.7. for the bit definitions default the I C interface operates in idle mode (M/IDL bit is ...
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I²C SINGLE MASTER BUS INTERFACE (Cont’d) Figure 64. Transfer Sequencing Master receiver: S Address A EV1 EV2 Master transmitter: S Address A EV1 EV2 EV4 Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV1: EVF=1, SB=1, cleared by ...
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ST7265x I²C SINGLE MASTER BUS INTERFACE (Cont’d) 11.7.5 Low Power Modes Mode 2 No effect interface. WAIT interrupts cause the device to exit from WAIT mode registers are frozen. 2 HALT ...
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I²C SINGLE MASTER BUS INTERFACE (Cont’d) 11.7.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h START ACK Bit 7:6 = Reserved. Forced hardware. Bit ...
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ST7265x I²C SINGLE MASTER BUS INTERFACE (Cont’ STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF 0 TRA 0 BTF Bit 7 = EVF Event flag. This bit is set by hardware as ...
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I²C SINGLE MASTER BUS INTERFACE (Cont’ STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h Bit 7:5 = Reserved. Forced hardware. Bit Acknowledge ...
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ST7265x Address Register 7 Name (Hex.) CCR FM/SM 43 Reset Value 0 DR DR7 46 Reset Value 0 114/163 CC6 CC5 CC4 DR6 DR5 DR4 CC3 CC2 CC1 ...
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A/D CONVERTER (ADC) 11.8.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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ST7265x 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.8.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input ...
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A/D CONVERTER (ADC) (Cont’d) 11.8.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 Bit 7 = COCO Conversion Complete This bit is set by hardware when a conversion is complete. ...
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ST7265x 8-BIT A/D CONVERTER (ADC) (Cont’d) Table 35. ADC Register Map and Reset Values Address Register 7 Label (Hex.) ADCDR D7 0012h Reset Value 0 ADCCSR COCO 0013h Reset Value 0 118/163 ...
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INSTRUCTION SET 12.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative ...
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ST7265x INSTRUCTION SET OVERVIEW (Cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait ...
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INSTRUCTION SET OVERVIEW (Cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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ST7265x INSTRUCTION SET OVERVIEW (Cont’d) 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and ...
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INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) ...
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ST7265x INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF ...
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ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum Values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ...
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ST7265x 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 13.2.1 Voltage Characteristics ...
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OPERATING CONDITIONS 13.3.1 General Operating Conditions Symbol Parameter Supply voltage with USB peripheral ena- bled Supply voltage with USB peripheral disa bled and LVD off (ROM version) Supply voltage with USB peripheral disa- bled and LVD off ...
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ST7265x OPERATING CONDITIONS (Cont’d) 13.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter Reset release threshold V IT+ (V rise) DD Reset generation threshold V IT- (V fall LVD voltage ...
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SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- vice consumption, the two current values ...
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ST7265x SUPPLY CURRENT CHARACTERISTICS (Cont’d) 13.4.2 WAIT Mode Symbol Parameter Supply current in WAIT mode (see Figure 72) I WFI Supply current in WAIT mode (see Figure 72) Figure 72. Typical I in WAIT vs ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 13.4.3 HALT Mode Symbol Parameter I Supply current in HALT mode HALT Notes: 1. All I/O pins in input mode with a static value USB Transceiver, USB voltage detector and ADC are powered ...
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ST7265x 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 13.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) 13.5.2 External Clock Source Symbol ...
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MEMORY CHARACTERISTICS Subject to general operating conditions for V 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 FLASH Memory Operating Conditions MHz. CPU DUAL VOLTAGE FLASH MEMORY Symbol Parameter f Operating ...
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ST7265x 13.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is ...
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... Dynamic latch-up class Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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ST7265x 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys I Input leakage current ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 76. V and V vs 3.5 3 2.5 2 1.5 1 0.5 0 2.5 3 Figure 77. Typical I vs -10 -20 -30 -40 -50 ...
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ST7265x I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 79 and ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 82.Typical V vs 0.35 0.3 0.25 0.2 0.15 0.1 0. Vdd (V) Figure 83. Typical V vs 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 ...
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ST7265x 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Output low level ...
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Figure 85. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01µF Figure 86. RESET pin protection when LVD is disabled. Recommended for EMC V DD 0.01µF USER EXTERNAL RESET CIRCUIT 0.01µF Required Note 1: – The reset network ...
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ST7265x CONTROL PIN CHARACTERISTICS (Cont’d) 13.9.2 V Pin PP Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Figure 87. Two typical Applications ...
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TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. OSC A 13.10.1 Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 13.10.2 PWM Generator Symbol Parameter T Repetition rate Res Resolution ...
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ST7265x 13.11 COMMUNICATION INTERFACE CHARACTERISTICS 13.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 89. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure 90. SPI Master ...
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ST7265x COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 13.11 Inter IC Control Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter t SCL clock low time w(SCLL) t SCL ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 13.11 Inter IC Control Interface Parameter Bus free time between a STOP and START con- dition Hold time START condition. After this period, the first clock pulse is generated LOW period of ...
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ST7265x COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 13.11.4 USB - Universal Bus Interface Parameter Input Levels: Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Output Levels Static Output Low Static Output High 3) USBV : voltage level CC Note ...
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ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Conversion range voltage AIN R External input resistor AIN C Internal sample and hold capacitor ADC t Stabilization time after ADC ...
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ST7265x 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter E Total Unadjusted Error T E Offset Error Gain Error Differential linearity error Integral linearity error L Figure 94. ADC Accuracy ...
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PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA Figure 95. 48-Pin Low profile Quad Flat Package D D1 Figure 96. 64-Pin Low profile Quad Flat Package θ 0.10mm ...
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ST7265x 14.2 THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax Notes: 1. The power dissipation is obtained from the formula P and P is the port power dissipation ...
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... SOLDERING INFORMATION In accordance with the RoHS European directive, all STMicroelectronics packages have been con- verted to lead-free technology, named ECO- TM PACK . TM ECOPACK packages are qualified according ■ to the JEDEC STD-020C compliant soldering profile. Detailed information on the STMicroelectronics ■ TM ECOPACK transition program is available on www ...
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ST7265x 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (ROM). FLASH devices are shipped to customers with a default content (FFh), while ROM ...
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... ST72F651AR6T1 ST72651AR6T1/xxx ST72652AR4T1/xxx ST72652C4T1/xxx ST72F651AR6T1E ST72651AR6T1E/xxx Note 1. /xxx stands for the ROM code name assigned by STMicroelectronics Note 2. Devices with E Suffix have no embedded LVD for more de- The customer code should be communicated to STMicroelectronics with the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points ...
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... Reference/ROM or FASTROM Code*:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *ROM or FASTROM code name is assigned by STMicroelectronics. ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. ...
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... The range of hardware tools includes full-featured ST7-EMU2B series emulators and the low-cost RLink in-circuit debugger/programmer. These tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7 in- tegrated development environment (IDE) with high-level language debugger, editor, project man- ager and integrated programming interface. ...
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ST7265x 15.4 ST7 APPLICATION NOTES Table 43. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION ...
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... AN1946 SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC AN1953 PFC FOR ST7MC STARTER KIT AN1971 ST7LITE0 MICROCONTROLLED BALLAST PROGRAMMING AND TOOLS AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 ...
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ST7265x Table 43. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ...
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... Devices configured with Hardware Watchdog must be programmed using a specific program- ming mode that ignores the option byte settings. In this mode, an external clock, normally provided by the programming tool, has to be used tools, this mode is called "ICP OPTIONS DISABLED". of devices Sockets on ST programming tools (such as ...
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... Updated final paragraph of References to 5V changed to V Additional note for USB cable unplug detection added, External interrupt text added, Development Tools, External power supply switch figure updated with new recommendation for PMOS page 33 TQFP packages renamed LQFP (Low profile Quad Flat) ...
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... Notes: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...