EVAL-AD7709EB Analog Devices Inc, EVAL-AD7709EB Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD7709EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7709EB

• Lead Free Status / Rohs Status: Compliant

AD7709
Configuration Register (A1, A0 = 0, 1; Power-On-Reset = 000007H)
The Configuration Register is a 24-bit register from which data can either be read or to which data can be written. This register is used to
select the input channel and configure the input range, excitation current sources, and I/O port. Table VII outlines the bit designations
for this register. CONFIG23 to CONFIG0 indicate the bit location, CONFIG denoting the bits are in the Configuration Register.
CONFIG23 denotes the first bit of the data stream. The number in brackets indicates the power-on-reset default status of that bit. A
write to the Configuration Register has immediate effect and does not reset the ADC. Therefore, if a current source is switched
while the ADC is converting, the user will have to wait for the full settling time of the sinc
This equates to three outputs.
Bit
Location
CONFIG23
CONFIG22
CONFIG21
CONFIG20
CONFIG19
CONFIG18
CONFIG17
R
R
R
R
R
C
C
C
C
C
C
C
C
C
C
C
P
P
P
P
P
P
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
4
S
S
S
S
S
F
F
F
F
F
N
N
N
N
N
D
N
N
N
N
W
W
W
W
W
N
N
S
S
S
S
S
F
F
F
F
F
F
I
F
F
F
F
F
E
E
E
E
E
( 2
( 2
( 2
( 2
( 2
G
I
I
I
I
I
I
I
I
I
I
I
L
L
L
L
L
G
G
G
G
G
G
(
G
G
G
G
G
) 0
) 0
) 0
) 0
) 0
(
(
(
(
(
) 0
3 2
3 2
3 2
3 2
3 2
5 1
) 0
) 0
) 0
7
7
7
7
7
) 0
) 0
PSW2
PSW1
I3EN1
I3EN0
I2EN1
I2EN0
I1EN1
Bit
Name
C
C
C
C
C
C
C
C
C
C
C
P
P
P
P
P
P
O
O
O
O
O
O
C
C
C
C
C
O
O
O
O
O
3
S
S
S
S
S
N
N
N
N
N
D
N
H
H
H
H
H
N
N
N
W
W
W
W
W
N
N
F
F
F
F
F
F
I
( 2
( 2
( 2
( 2
( 2
F
F
F
F
F
( 1
( 1
( 1
( 1
( 1
G
I
I
I
I
I
I
I
I
I
I
I
Description
Power Switch 2 Control Bit.
Set by user to enable power switch SW2/P2 to PWRGND.
Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches
are open.
Power Switch 1 Control Bit.
Set by user to enable power switch SW1/P1 to PWRGND.
Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches
are open.
IEXC3 Current Source Enable Bit
IEXC3 Current Source Enable Bit
IEXC2 Current Source Enable Bit
IEXC2 Current Source Enable Bit
IEXC1 Current Source Enable Bit
G
G
G
G
G
) 0
) 0
) 0
) 0
) 0
I3EN1
0
0
1
1
I2EN1
0
0
1
1
G
(
G
G
G
G
G
) 0
) 0
) 0
) 0
) 0
) 0
2 2
2 2
2 2
2 2
2 2
4 1
6
6
6
6
6
C
C
C
C
C
C
C
C
C
C
C
3 I
3 I
3 I
3 I
3 I
O
O
O
O
O
P
O
C
C
C
C
C
O
O
O
O
O
E
E
E
E
E
2
N
N
N
N
N
H
H
H
H
H
N
N
N
N
Table VII. Configuration Register Bit Designations
N
N
E
N
N
N
N
N
F
F
F
F
F
F
( 1
( 1
( 1
( 1
( 1
F
F
F
F
F
N
( 1
( 1
( 1
( 1
( 1
I
I
I
I3EN0
0
1
0
1
I2EN0
0
1
0
1
I
I
I
I
I
I
I
I
G
G
G
G
G
(
) 0
) 0
) 0
) 0
) 0
G
G
G
G
G
G
) 0
) 0
) 0
) 0
) 0
) 0
1 2
1 2
1 2
1 2
1 2
3 1
5
5
5
5
5
C
C
C
C
C
C
C
C
C
C
C
3 I
3 I
3 I
3 I
3 I
O
O
O
O
O
P
O
C
C
C
C
C
O
O
O
O
O
Function
IEXC3 Current Source OFF
IEXC3 Current Source Routed to the IOUT1 Pin
IEXC3 Current Source Routed to the IOUT2 Pin
Reserved
Function
IEXC2 Current Source OFF
IEXC2 Current Source Routed to the IOUT1 Pin
IEXC2 Current Source Routed to the IOUT2 Pin
Reserved
E
E
E
E
E
1
N
N
N
N
N
H
H
H
H
H
N
N
N
N
N
N
E
N
N
N
N
N
F
F
F
F
F
F
( 0
( 0
( 0
( 0
( 0
F
F
F
F
F
N
( 0
( 0
( 0
( 0
( 0
I
I
I
I
I
I
I
I
I
I
I
G
G
G
(
) 0
) 0
) 0
G
G
) 0
) 0
G
G
G
G
G
G
) 0
) 0
) 0
) 0
) 0
) 0
0 2
0 2
0 2
0 2
0 2
2 1
4
4
4
4
4
–16–
C
C
C
C
C
C
C
C
C
C
C
P
2 I
2 I
2 I
2 I
2 I
O
O
O
O
O
O
4
O
O
O
O
O
U
E
E
E
E
E
D
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
F
F
F
F
F
A
F
( I
F
F
F
F
F
( 1
( 1
( 1
( 1
( 1
I
I
I
I
I
I
T
I
I
I
I
I
) 0
G
G
G
G
G
G
G
G
G
G
G
) 0
) 0
) 0
) 0
) 0
(
9 1
9 1
9 1
9 1
9 1
) 0
1 1
3
3
3
3
3
C
C
C
C
C
C
C
C
C
C
C
P
3
2 I
2 I
2 I
2 I
2 I
O
O
O
O
O
O
R
3
O
O
O
O
O
filter before obtaining a fully settled output.
E
E
E
E
E
D
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
F
F
F
F
F
A
F
( 2
F
F
F
F
F
( 0
( 0
( 0
( 0
( 0
I
I
I
I
I
I
T
I
I
I
I
I
G
G
G
) 1
G
G
G
G
G
G
G
G
) 0
) 0
) 0
) 0
) 0
(
8 1
8 1
8 1
8 1
8 1
) 0
0 1
2
2
2
2
2
C
C
C
C
C
C
C
C
C
C
C
P
1 I
1 I
1 I
1 I
1 I
O
O
O
O
O
2
O
O
O
O
O
R
O
E
E
E
E
E
D
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
F
F
F
F
F
A
( 1
F
F
F
F
F
F
( 1
( 1
( 1
( 1
( 1
I
I
I
I
I
T
I
I
I
I
I
G
G
G
I
) 1
G
G
G
G
G
G
G
) 0
) 0
) 0
G
) 0
) 0
(
7 1
7 1
7 1
7 1
7 1
) 0
1
1
1
1
1
9
C
C
C
C
C
C
C
C
C
C
C
P
1 I
1 I
1 I
1 I
1 I
O
O
O
O
O
1
O
O
O
O
O
R
O
E
E
E
E
E
D
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
F
F
F
F
F
A
( 0
F
F
F
F
F
F
( 0
( 0
( 0
( 0
( 0
REV. A
I
I
I
I
I
T
I
I
I
I
I
I
) 1
G
G
G
G
G
G
G
G
G
G
) 0
) 0
) 0
G
) 0
) 0
(
6 1
6 1
6 1
6 1
6 1
) 0
0
0
0
0
0
8