EVAL-AD7709EB Analog Devices Inc, EVAL-AD7709EB Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD7709EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7709EB

• Lead Free Status / Rohs Status: Compliant

AD7709
TIMING CHARACTERISTICS
Parameter
t
t
Read Operation
Write Operation
NOTES
1
2
3
4
5
6
7
1
2
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figures 2 and 3.
SCLK active edge is falling edge of SCLK.
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
This specification comes into play only if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics table are the true bus relinquish
times of the part and as such are independent of external bus loading capacitances.
RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur
close to the next output update.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3
4
5
5A
6
7
8
9
10
11
12
13
14
15
16
4
6
4, 5
Limit at T
(A, B Version)
30.5176
50
0
0
0
60
80
0
60
80
100
100
0
10
80
100
0
30
25
100
100
0
MIN
1, 2
, T
MAX
(V
Logic 1 = V
DD
= 2.7 V to 3.6 V or V
DD
unless otherwise noted.)
Unit
ms
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
typ
–6–
DD
= 4.75 V to 5.25 V; GND = 0 V; X
R
= t
F
= 5 ns (10% to 90% of V
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Active Edge to RDY High
SCLK High Pulsewidth
SCLK Low Pulsewidth
Conditions/Comments
Crystal Oscillator Period
RESET Pulsewidth
RDY to CS Setup Time
CS Falling Edge to SCLK Active Edge Setup Time
SCLK Active Edge to Data Valid Delay
V
V
CS Falling Edge to Data Valid Delay
V
V
CS Rising Edge to SCLK Inactive Edge Hold Time
Bus Relinquish Time after SCLK Inactive Edge
CS Falling Edge to SCLK Active Edge Setup Time
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
CS Rising Edge to SCLK Edge Hold Time
DD
DD
DD
DD
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
OL
DD
or V
) and timed from a voltage level of 1.6 V.
OH
TAL
limits.
= 32.768 kHz; Input Logic 0 = 0 V,
3, 7
3
REV. A
3
3
3
3