MC145193F Freescale Semiconductor, MC145193F Datasheet - Page 11

• Manufacturer Part Number: MC145193F
• Manufacturer: Freescale Semiconductor

Specifications of MC145193F

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SO
• Pin Count: 20
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PD out
Single–Ended Phase/Frequency Detector Output (Pin 6)
a loop error signal when combined with an external low–pass
filter. The phase/frequency detector is characterized by a
linear transfer function. The operation of the
phase/frequency detector is described below and is shown in
Figure 17.
C register. If desired, PD out can be forced to the
high–impedance state by utilization of the disable feature in
the C register (bit C6). This is a patented feature. Similarly,
PD out is forced to the high–impedance state when the device
is put into standby (STBY bit C4 = high).
gain is controllable by bits C3, C2, and C1: gain (in amps per
radian) = PD out current divided by 2 .
Double–Ended Phase/Frequency Detector Outputs
loop error signal. Through use of a Motorola patented
technique, the detector’s dead zone has been eliminated.
Therefore, the phase/frequency detector is characterized by
a li near t r ans f er fun c tio n. The op er at ion o f th e
phase/frequency detector is described below and is shown in
Figure 17.
interchanged via C register bits C6 or C4. This is a patented
R and V (Pins 3 and 4)
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
This is a three–state current–source/sink output for use as
Frequency of f V > f R or Phase of f V Leading f R :
Frequency of f V < f R or Phase of f V Lagging f R :
Frequency and Phase of f V = f R : essentially a floating
POL bit (C7) = high
Frequency of f V > f R or Phase of f V Leading f R :
Frequency of f V < f R or Phase of f V Lagging f R :
Frequency and Phase of f V = f R : essentially a floating
Frequency of f V > f R or Phase of f V Leading f R : V =
Frequency of f V < f R or Phase of f V Lagging f R : V =
Frequency and Phase of f V = f R : V and R remain
POL bit (C7) = high
Frequency of f V > f R or Phase of f V Leading f R : R =
Frequency of f V < f R or Phase of f V Lagging f R : R =
Frequency and Phase of f V = f R : V and R remain
These outputs can be enabled, disabled, and
POL bit (C7) in the C register = low (see Figure 14)
This output can be enabled, disabled, and inverted via the
The PD out circuit is powered by V PD . The phase detector
These outputs can be combined externally to generate a
POL bit (C7) in the C register = low (see Figure 14)
current–sinking pulses from a floating state
current–sourcing pulses from a floating state
state; voltage at pin determined by loop filter
current–sourcing pulses from a floating state
current–sinking pulses from a floating state
state; voltage at pin determined by loop filter
negative pulses, R = essentially high
essentially high, R = negative pulses
essentially high, except for a small minimum time period
when both pulse low in phase
negative pulses, V = essentially high
essentially high, V = negative pulses
essentially high, except for a small minimum time period
when both pulse low in phase
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MC145193
feature. Note that when disabled or in standby, R and V are
forced to their rest condition (high state).
Gnd to V PD .
LD
Lock Detector Output (Pin 2)
low–going pulses when the loop is locked (f R and f V of the
same phase and frequency). The output pulses low when f V
and f R are out of phase or different frequencies. LD is the
logical ANDing of R and V (see Figure 17).
This is a patented feature. Upon power up, on–chip
initialization circuitry disables LD to a static low logic level to
prevent a false “lock” signal. If unused, LD should be disabled
and left open.
V DD .
Rx
External Resistor (Pin 8)
with bits in the C register, determines the amount of current
that the PD out pin sinks and sources. When bits C2 and C3
are both set high, the maximum current is obtained at PD out ;
see Tables 4 and 5 for other current values. The
recommended value for Rx is 3.9 k (preliminary) . A value of
3.9 k
mA @ V DD = 3 V and approximately 1.7 mA @ V DD = 5 V in
the 100% current mode. Note that V DD , not V PD , is a factor in
determining the current.
floated.
The R and V output signal swing is approximately from
This output is essentially at a high level with narrow
This output can be enabled and disabled via the C register.
The LD output signal swing is approximately from Gnd to
A resistor tied between this pin and Gnd, in conjunction
When the R and V outputs are used, the Rx pin may be
* At the time the data sheet was printed, only the 100%
* At the time the data sheet was printed, only the 100%
current mode was guaranteed. The reduced current
modes were for experimentation only.
current mode was guaranteed. The reduced current
modes were for experimentation only.
provides current at the PD out pin of approximately 1
Table 5. PD out Current*, C1 = High with
Table 4. PD out Current*, C1 = Low with
Bit C3
Bit C3
Also, Default Mode When Output A
Output A not Selected as “Port”;
Output A not Selected as “Port”
0
0
1
1
0
0
1
1
Selected as “Port”
Bit C2
Bit C2
0
1
0
1
0
1
0
1
PD out Current*
PD out Current*
100%
100%
70%
80%
90%
25%
50%
75%
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