CAT5251YI-50-TE13 ON Semiconductor, CAT5251YI-50-TE13 Datasheet - Page 3

• Manufacturer Part Number: CAT5251YI-50-TE13
• Manufacturer: ON Semiconductor

Specifications of CAT5251YI-50-TE13

• Number Of Elements: 4
• # Of Taps: 256
• Resistance (max): 50KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (SPI)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 6V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Compliant

Pin Descriptions
SI: Serial Input
opcodes, byte addresses and data to be written to the
CAT5251. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
data out of the CAT5251. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
the communication between the microcontroller and the
CAT5251. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5251.
R
terminal connections on a mechanical potentiometer.
R
a mechanical potentiometer.
H
W
SI is the serial data input pin. This pin is used to input all
SO is the serial data output pin. This pin is used to transfer
SCK is the serial clock pin. This pin is used to synchronize
These inputs set the device address when addressing
The four sets of R
The four R
, R
: Wiper
L
: Resistor End Points
W
pins are equivalent to the wiper terminal of
H
and R
HOLD
SCK
WP
CS
SO
A0
A1
SI
L
pins are equivalent to the
INTERFACE
CONTROL
SPI BUS
LOGIC
Figure 1. Functional Diagram
http://onsemi.com
NONVOLATILE
REGISTERS
REGISTERS
CONTROL
WIPER
DATA
3
CS: Chip Select
and CS high disables the CAT5251. CS high takes the SO
output pin to high impedance and forces the devices into a
Standby mode (unless an internal write operation is
underway). The CAT5251 draws ZERO current in the
Standby mode. A high to low transition on CS is required
prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what initiates
an internal write cycle.
WP: Write Protect
allow normal read/write operations when held high. When
WP is tied low, all non−volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP going low will have no effect on any write
operation.
HOLD: Hold
CAT5251 while in the middle of a serial sequence without
having to re−transmit entire sequence at a later time. To
pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part
is paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD is brought high, while SCK
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to V
tied to V
CS is the Chip select pin. CS low enables the CAT5251
WP is the Write Protect pin. The Write Protect pin will
The HOLD pin is used to pause transmission to the
R
R
CC
H0
L0
through a resistor.
R
R
H1
L1
R
R
H2
L2
R
R
H3
L3
R
R
R
R
W0
W1
W2
W3
CC
or