AD9238BCP40EB Analog Devices Inc, AD9238BCP40EB Datasheet

no-image

AD9238BCP40EB

Manufacturer Part Number
AD9238BCP40EB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9238BCP40EB

Lead Free Status / Rohs Status
Not Compliant
FEATURES
Integrated dual 12-bit ADC
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dB (to Nyquist, AD9238-65)
SFDR = 80.5 dBc (to Nyquist, AD9238-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option
APPLICATIONS
Ultrasound equipment
Direct conversion or IF sampling receivers
Battery-powered instruments
Hand-held scopemeters
Low cost, digital oscilloscopes
GENERAL DESCRIPTION
The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and-hold amplifiers (SHAs) and an
integrated voltage reference. The AD9238 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch full-
scale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
WB-CDMA, CDMA2000, WiMAX
12-Bit, 20 MSPS/40 MSPS/65 MSPS
Fabricated on an advanced CMOS process, the AD9238 is
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C).
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9248, 14-bit 20MSPS/
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
3. Low power consumption:
4. Typical channel isolation of 85 dB @ f
5. The clock duty cycle stabilizer (AD9238-20/AD9238-40/
6. Multiplexed data output option enables single-port operation
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
REFB_B
REFB_A
REFT_B
REFT_A
VIN+_B
VIN–_B
VIN+_A
VIN–_A
SENSE
AGND
VREF
40 MSPS/65 MSPS ADC.
allow flexibility between power, cost, and performance to suit
an application.
AD9238-65) maintains performance over a wide range of
clock duty cycles.
from either Data Port A or Data Port B.
AD9238-65: 65 MSPS = 600 mW
AD9238-40: 40 MSPS = 330 mW
AD9238-20: 20 MSPS = 180 mW
AD9238
FUNCTIONAL BLOCK DIAGRAM
SHA
SHA
0.5V
©2005 Analog Devices, Inc. All rights reserved.
Dual A/D Converter
ADC
DRVDD DRGND
ADC
AVDD
Figure 1.
12
12
AGND
DUTY CYCLE
STABILIZER
BUFFERS
BUFFERS
CONTROL
OUTPUT
OUTPUT
CLOCK
MODE
MUX/
MUX/
IN
= 10 MHz.
12
12
www.analog.com
AD9238
MUX_SELECT
CLK_A
DCS
SHARED_REF
PWDN_A
DFS
D11_B TO D0_B
OTR_A
CLK_B
PWDN_B
OTR_B
D11_A TO D0_A
OEB_A
OEB_B

AD9238BCP40EB Summary of contents

Page 1

FEATURES Integrated dual 12-bit ADC Single 3 V supply operation (2 3.6 V) SNR = 70 dB (to Nyquist, AD9238-65) SFDR = 80.5 dBc (to Nyquist, AD9238-65) Low power: 300 mW/channel at 65 MSPS Differential input with 500 ...

Page 2

AD9238 TABLE OF CONTENTS Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 6 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ........................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 ...

Page 3

Rev. A Changes to DC Specifications ........................................................ 2 Changes to Switching Specifications ............................................. 3 Changes to AC Specifications......................................................... 4 Changes to Figure 1.......................................................................... 4 Changes to Ordering Guide............................................................ 5 Changes to TPCs 2, 3, and 6 ........................................................... ...

Page 4

AD9238 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B DCS enabled, unless otherwise noted. MIN MAX Table 1. Parameter Temp RESOLUTION Full ACCURACY No Missing Codes ...

Page 5

AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B DCS enabled, unless otherwise noted. MIN MAX Table 2. Parameter SIGNAL-TO-NOISE RATIO (SNR 2.4 MHz INPUT f ...

Page 6

AD9238 DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B DCS enabled, unless otherwise noted. MIN MAX Table 3. Parameter Temp LOGIC INPUTS High Level Input Voltage Full ...

Page 7

ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Pin Name ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF OEB, DFS VINA, VINB VREF SENSE REFB, REFT PDWN 2 ENVIRONMENTAL Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature ...

Page 8

AD9238 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND VIN+_A VIN–_A AGND AVDD REFT_A REFB_A VREF SENSE REFB_B REFT_B AVDD AGND VIN–_B VIN+_B AGND PIN ...

Page 9

Table 6. Pin Function Descriptions (64-Lead LQFP and 64-Lead LFCSP) Pin No. Mnemonic Description 1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN–_A Analog Input Pin (−) for Channel A. 5, ...

Page 10

AD9238 TERMINOLOGY Aperture Delay SHA performance measured from the rising edge of the clock input to when the input signal is held for conversion. Aperture Jitter The variation in aperture delay for successive samples, which is manifested as noise on ...

Page 11

TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3 25° –20 –40 –60 SECOND HARMONIC –80 CROSSTALK –100 –120 FREQUENCY (MHz) Figure 4. Single-Tone FFT of Channel A Digitizing f While ...

Page 12

AD9238 100 –35 –30 –25 –20 –15 INPUT AMPLITUDE (dBFS) Figure 10. AD9238-65 Single-Tone SNR/SFDR vs. AIN with f 100 90 80 SNR SFDR 70 SNR SNR –35 –30 –25 –20 ...

Page 13

FREQUENCY (MHz) Figure 16. Dual-Tone FFT with MHz and –20 –40 –60 –80 –100 –120 FREQUENCY ...

Page 14

AD9238 74 72 SINAD –20 70 SINAD – CLOCK FREQUENCY Figure 22. SINAD vs. FS with Nyquist Input 95 DCS ON (SFDR DCS OFF (SFDR DCS OFF (SINAD ...

Page 15

EQUIVALENT CIRCUITS AVDD VIN+_A, VIN–_A, VIN+_B, VIN–_B Figure 28. Equivalent Analog Input Circuit DRVDD Figure 29. Equivalent Digital Output Circuit AVDD CLK_A, CLK_B DCS, DFS, MUX_SELECT, SHARED_REF Figure 30. Equivalent Digital Input Circuit Rev Page ...

Page 16

AD9238 THEORY OF OPERATION The AD9238 consists of two high performance ADCs that are based on the AD9235 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC ...

Page 17

The minimum common-mode input level allows the AD9238 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single- ended source may be driven into VIN+ or VIN−. In this configuration, one input accepts the signal, ...

Page 18

AD9238 (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. POWER DISSIPATION AND STANDBY MODE The power dissipated by the AD9238 is proportional to its sampling rates. The digital (DRVDD) power ...

Page 19

DATA FORMAT The AD9238 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to ...

Page 20

AD9238 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may ...

Page 21

AD9238 LQFP EVALUATION BOARD The evaluation board supports both the AD9238 and AD9248 and has five main sections: clock circuitry, inputs, reference circuitry, digital control logic, and outputs. A description of each section follows. Table 8 shows the jumper settings ...

Page 22

AD9238 Table 8. PCB Jumpers Normal JP Description Setting Comment 1 Reference Out 1 V Reference Mode 2 Reference Reference Mode 3 Reference Out 1 V Reference Mode 4 Reference Out 1 V Reference Mode 5 Reference ...

Page 23

LQFP EVALUATION BOARD BILL OF MATERIALS (BOM) Table 10. No. Quantity Reference Designator 1 18 C1, C2, C11, C12, C27, C28, C33, C34, C50, C51, C73 to C76, C87 to C90 C10, C29 to C31, C56, ...

Page 24

AD9238 LQFP EVALUATION BOARD SCHEMATICS Figure 39. Evaluation Board Schematic Rev Page ...

Page 25

Figure 40. Evaluation Board Schematic (Continued) Rev Page AD9238 ...

Page 26

AD9238 Figure 41. Evaluation Board Schematic (Continued) Rev Page ...

Page 27

C75 C3 C10 C9 C8 10µF 0.1µF 0.1µF 0.1µF 0.1µF 6. DATACLKA 19 U10 G2 74VHC541 1 RP9 22Ω RP9 22Ω OTRA RP9 22Ω DA13 4 RP9 ...

Page 28

AD9238 LQFP PCB LAYERS Figure 43. PCB Top Side Silkscreen Rev Page ...

Page 29

Figure 44. PCB Top Layer Rev Page AD9238 ...

Page 30

AD9238 Figure 45. PCB Ground Plane Rev Page ...

Page 31

Figure 46. PCB Split Power Plane Rev Page AD9238 ...

Page 32

AD9238 Figure 47. PCB Bottom Layer Rev Page ...

Page 33

Figure 48. PCB Bottom Silkscreen Rev Page AD9238 ...

Page 34

AD9238 1 DUAL ADC LFCSP PCB The PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with ADI’s standard dual-channel data capture board (HSC-ADC-EVAL-DC), which together with ADI’s ADC Analyzer™ software allows for ...

Page 35

LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) Table 13. No. Quantity Reference Designator C2, C5, C7, C9, C10, C22, C36 3 44 C4, C6, C8, C11 to C15, C20, C21, C24 to C27, C29 ...

Page 36

AD9238 LFCSP PCB SCHEMATICS ENCA D7A D7_A 49 D8A D8_A 50 D9A D9_A 51 DRVDD2 52 DRGND2 53 D10A D10_A 54 D11A D11_A 55 D12A D12_A 56 D13A D13_A 57 OTRA OTR_A 58 OEB_A 59 PDWN_A 60 MUX_SEL 61 SH_REF ...

Page 37

Figure 50. PCB Schematic ( Rev Page AD9238 ...

Page 38

AD9238 Figure 51. PCB Schematic ( Rev Page ...

Page 39

LFCSP PCB LAYERS Figure 52. PCB Top-Side Silkscreen Rev Page AD9238 ...

Page 40

AD9238 Figure 53. PCB Top-Side Copper Routing Rev Page ...

Page 41

Figure 54. PCB Ground Layer Rev Page AD9238 ...

Page 42

AD9238 Figure 55. PCB Split Power Plane Rev Page ...

Page 43

Figure 56. PCB Bottom-Side Copper Routing Rev Page AD9238 ...

Page 44

AD9238 THERMAL CONSIDERATIONS The AD9238 LFCSP has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane ...

Page 45

OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 9.00 BSC SQ PIN 1 INDICATOR TOP VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE 0.75 1.60 0.60 MAX 0. PIN 1 0.20 0.09 ...

Page 46

AD9238 ORDERING GUIDE Model Temperature Range AD9238BST-20 –40°C to +85°C AD9238BSTRL-20 –40°C to +85°C 1 AD9238BSTZ-20 –40°C to +85°C 1 AD9238BSTZRL-20 –40°C to +85°C 1 AD9238BSTZ-20EB AD9238BST-40 –40°C to +85°C AD9238BSTRL-40 –40°C to +85°C 1 AD9238BSTZ-40 –40°C to +85°C 1 ...

Page 47

NOTES Rev Page AD9238 ...

Page 48

AD9238 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02640–0–4/05(B) Rev Page ...