DS90CF561MTD National Semiconductor, DS90CF561MTD Datasheet
DS90CF561MTD
Specifications of DS90CF561MTD
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DS90CF561MTD Summary of contents
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... LCD panel controllers. Block Diagrams DS90CF561 Order Number DS90CF561MTD See NS Package Number MTD48 © 2000 National Semiconductor Corporation This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. ...
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Connection Diagrams DS90CF561 www.national.com DS012485-3 2 DS90CF562 DS012485-4 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Ouput Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter TRANSMITTER SUPPLY CURRENT I Transmitter Supply Current, CCTZ Power Down RECEIVER SUPPLY CURRENT I Receiver Supply Current, CCRW Worst Case I Receiver Supply Current, CCRG 16 ...
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Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol TCCD TxCLK IN to TxCLK OUT Delay V = 5.0V ( Figure Transmitter Phase Lock Loop Set ( Figure 11 ) TPLLS TPDD ...
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AC Timing Diagrams FIGURE 2. “16 Grayscale” Test Pattern (Notes 10) Note 7: The worst case test pattern produces a maximum toggling of device digital circuitry, LVDS I/O and TTL I/O. Note 8: The 16 grayscale test ...
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AC Timing Diagrams (Continued) Measurements at Vdiff = 0V TCCS measured between earliest and latest initial LVDS edges. TxCLK OUT Differential High Low Edge for DS90CF561 TxCLK OUT Differential Low High Edge for DS90CR561 FIGURE 6. DS90CF561 (Transmitter) Channel-to-Channel Skew ...
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AC Timing Diagrams FIGURE 10. DS90CF562 (Receiver) Clock In to Clock Out Delay FIGURE 11. DS90CF561 (Transmitter) Phase Lock Loop Set Time FIGURE 12. DS90CF562 (Receiver) Phase Lock Loop Set Time FIGURE 13. Seven Bits of LVDS in One Clock ...
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AC Timing Diagrams (Continued) FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF561) FIGURE 15. Transmitter Powerdown Delay FIGURE 16. Receiver Powerdown Delay 9 DS012485-21 DS012485-22 DS012485-23 www.national.com ...
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AC Timing Diagrams FIGURE 17. Transmitter LVDS Output Pulse Position Measurement SW — Setup and Hold Time (Internal Data Sampling Window) TCCS — Transmitter Output Skew RSKM Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle) Cable Skew ...
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DS90CF561 Pin Description—FPD Link Transmitter Pin Name I/O No. TxIN I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE, FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.) TxOUT+ ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...