CY7C4245-15JC Cypress Semiconductor Corp, CY7C4245-15JC Datasheet - Page 7

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CY7C4245-15JC

Manufacturer Part Number
CY7C4245-15JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4245-15JC

Configuration
Dual
Density
72Kb
Access Time (max)
10ns
Word Size
18b
Organization
4Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
45mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Lead Free Status / Rohs Status
Not Compliant
Switching Waveforms
Notes:
14. .t
15. The clocks (RCLK, WCLK) can be free-running during reset.
16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
Read Cycle Timing
Reset Timing
REN, WEN,
Q
Q
rising edge of WCLK and the rising edge of RCLK is less than t
0
EF,PAE
FF,PAF,
WCLK
0 -
SKEW2
RCLK
–Q
WEN
REN
OE
EF
RS
Q
17
HF
LD
17
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
[15]
t
ENS
t
OLZ
(continued)
t
ENH
t
CLKH
t
t
A
REF
t
t
t
RSF
RSF
RSF
t
OE
t
RS
t
CLK
t
SKEW2
SKEW2
NO OPERATION
, then EF may not change state until the next RCLK edge.
[14]
t
CLKL
7
VALID DATA
t
RSR
t
REF
t
OHZ
CY7C4425/4205/4215
CY7C4225/4235/4245
OE=0
OE=1
[16]
42X5–7
42X5–8

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