DS15BR400EVK National Semiconductor, DS15BR400EVK Datasheet - Page 3

• Manufacturer Part Number: DS15BR400EVK
• Manufacturer: National Semiconductor

Specifications of DS15BR400EVK

• Lead Free Status / Rohs Status: Supplier Unconfirmed

DIFFERENTIAL INPUTS
IN0+
IN0−
IN1+
IN1−
IN2+
IN2−
IN3+
IN3−
DIFFERENTIAL OUTPUTS
OUT0+
OUT0−
OUT1+
OUT1−
OUT2+
OUT2−
OUT3+
OUT3-
DIGITAL CONTROL INTERFACE
PWDN
PEM
POWER
V
GND
N/C
Name
DD
Pin Descriptions
Note 1: Note that for the LLP package the GND is connected thru the DAP on the back side of the LLP package in addition to the actual pin numbers listed.
Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15BR400 and DS15BR401 are optimized
for point-to-point backplane and cable applications.
Pin
3, 4, 5, 7, 10, 11,
8, 9, 17, 18, 23,
1,6, 25, 26, 27,
24, 37, 38, 43,
30, 31, 34, 35,
28, 29, 32, 33
TQFP Pin
Number
13
14
15
16
19
20
21
22
48
47
46
45
42
41
40
39
12
44
36
2
3, 4, 6, 7, 20,
18,19,22, 23,
5 (Note 1)
Number
LLP Pin
1, 17,
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
21
24
9
8
2
I/O, Type
I, Ground
O, LVDS
O, LVDS
O, LVDS
O, LVDS
I, LVTTL
I, LVTTL
I, Power
I, LVDS
I, LVDS
I, LVDS
I, LVDS
Channel 0 inverting and non-inverting differential inputs.
Channel 1 inverting and non-inverting differential inputs.
Channel 2 inverting and non-inverting differential inputs.
Channel 3 inverting and non-inverting differential inputs.
Channel 0 inverting and non-inverting differential outputs. (Note 2)
Channel 1 inverting and non-inverting differential outputs. (Note 2)
Channel 2 inverting and non-inverting differential outputs. (Note 2)
Channel 3 inverting and non-inverting differential outputs. (Note 2)
A logic low at PWDN activates the hardware power down mode (all channels).
Pre-emphasis Control Input (affects all Channels)
V
Ground reference for LVDS and CMOS circuitry. For the LLP package, the DAP
is used as the primary GND connection to the device in addition to the pin
numbers listed. The DAP is the exposed metal contact at the bottom of the
LLP-32 package. It should be connected to the ground plane with at least 4
vias for optimal AC and thermal performance.
No Connect
DD
= 3.3V, ±10%
3
Description
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