DS15BR400EVK National Semiconductor, DS15BR400EVK Datasheet - Page 5

• Manufacturer Part Number: DS15BR400EVK
• Manufacturer: National Semiconductor

Specifications of DS15BR400EVK

• Lead Free Status / Rohs Status: Supplier Unconfirmed

LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
V
ΔV
V
ΔV
C
I
SUPPLY CURRENT (Static)
I
I
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t
t
t
t
t
t
t
t
t
t
Symbol
OS
CC
CCZ
LHT
HLT
PLHD
PHLD
SKD1
SKCC
SKP
JIT
ON
OFF
OD
OS
OUT
Note 5: Typical parameters are measured at V
Note 6: Differential output voltage V
Note 7: Output offset voltage V
Note 8: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 9: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. Stimulus and fixture Jitter has been subtracted. The
input voltage = V
Note 10: Deterministic Jitter, or DJ, is a peak to peak value. Stimulus and fixture jitter has been subtracted. The input voltage = V
mode voltage = V
Note 11: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input
voltage = V
Note 12: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization.
OD
OS
Differential Output Voltage,
0% Pre-emphasis (Note 6)
Change in V
Complementary States
Offset Voltage (Note 7)
Change in V
Complementary States
LVDS Output Capacitance
Output Short Circuit Current
Supply Current
Supply Current - Power Down
Mode
Differential Low to High
Transition Time (Note 12)
Differential High to Low
Transition Time (Note 12)
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Pulse Skew (Note 12)
Output Channel to Channel
Skew (Note 12)
Part to Part Skew (Note 12)
Jitter (0% Pre-emphasis)
(Note 8)
LVDS Output Enable Time
LVDS Output Disable Time
ID
= 500 mV, input common mode voltage = V
ID
ICM
= 500 mV, input common mode voltage = V
Parameter
= 1.2V, K28.5 pattern at 1.5 Gbps, t
OD
OS
between
between
OS
is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
OD
is defined as ABS(OUT+–OUT−). Differential input voltage V
DD
R
Figure 1
OUT+ or OUT− to V
OUT+ or OUT− Short to GND
OUT+ or OUT− Short to VDD
All inputs and outputs enabled and active, terminated with
differential load of 100Ω between OUT+ and OUT-. PEM =
L
PWDN = L, PEM = L
Use an alternating 1 and 0 pattern at 200 Mbps, measure
between 20% and 80% of V
Figures 2, 4
Use an alternating 1 and 0 pattern at 200 Mbps, measure
at 50% V
Figures 2, 3
|t
Difference in propagation delay (t
output channels.
Common edge, parts at same temp and V
RJ - Alternating 1 and 0 at 750 MHz (Note 9)
DJ - K28.5 Pattern, 1.5 Gbps (Note 10)
TJ - PRBS 2
Time from PWDN to OUT± change from TRI-STATE to
active.
Figures 5, 6
Time from PWDN to OUT± change from active to TRI-
STATE.
Figures 5, 6
PLHD
L
= 3.3V, T
= 100Ω external resistor between OUT+ and OUT−
–t
PHLD
r
ICM
= t
OD
A
f
= 25°C. They are for reference purposes, and are not production-tested.
= 1.2V, 2
= 50 ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
|
between input to output.
ICM
23
-1 Pattern, 1.5 Gbps (Note 11)
= 1.2V, 50% duty cycle at 750 MHz, t
23
-1 PRBS pattern at 1.5 Gbps, t
SS
Conditions
5
OD
.
PLHD
or t
PHLD
CC
ID
is defined as ABS(IN+–IN−).
r
r
= t
) among all
= t
f
f
= 50 ps (20% to 80%).
= 50 ps (20% to 80%).
1.05
Min
250
−35
−35
ID
= 500 mV, input common
(Note
1.18
Typ
360
−21
175
170
170
2.5
1.0
1.0
0.5
20
10
25
14
14
5)
6
1.475
Max
500
−40
215
200
250
250
550
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2.0
2.0
1.5
35
35
40
60
75
30
31
20
12
Units
mV
mV
mV
mA
mA
mA
pF
µA
ps
ps
ns
ns
ps
ps
ps
ps
ps
ps
µs
ns
V