SD130EVK/NOPB National Semiconductor, SD130EVK/NOPB Datasheet - Page 3

• Manufacturer Part Number: SD130EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of SD130EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

Multiplexing ACLK as Chip-select
Write and Read Cycle Timing
However the multiplexing function is implemented, it is im-
portant to avoid decode glitches which might cause false or
multiple A
than one device. The design of the multiplexer logic must
make suitable allowance to assure that the propagation of all
select inputs, such as S0, S1 and BROADCAST, to the
decoded outputs remains stable from the falling edge of
A
address load operation. The select decode process must be
completed before A
operation, this is shown in Figure 3. Addition of a broadcast
function places additional timing constraints on the logic
which must be accommodated in the timing margin allow-
ance. The select logic must remain stable during both the
register address and the subsequent data read or write
operations which comprise the complete access cycle.
Note that the setup and hold times of the AD port data with
respect to the rising edge of A
defined in the data sheet AC Specifications of the respective
device.
CLK
to the next rising edge which initiates the register
CLK
pulses or overlapping A
CLK
is asserted. For the complete write
CLK
FIGURE 2. A
are those timing values
CLK
cycles to more
CLK
Control Logic with Broadcast Mode
(Continued)
3
The write operation begins with an address load cycle. The
control inputs ANC/CTRL and RD/WR are set appropriately.
It is recommended that these control signals be changed
coincident with the falling edge of A
should be fully stable a suitable time before the rising edge
of A
which ends the data load portion of the operation.
The read operation, Figure 4, begins with an address load
cycle in the same manner as the write operation. The
RD/WR control is set to the read mode. Once the register
address is strobed into the port, the device driving the port
must release the port in order for the device to drive the
register’s data as output. The data will appear and be driven
by the port after an internal propagation delay of about
8.5ns. The port will remain in the output mode until the next
rising edge of A
receive mode pending the input of the next register address.
Care should be taken to avoid prolonged periods of bus
contention between the AD port and external drivers.
CLK
and remain stable until after the falling edge of A
CLK
releases the port and returns it to the
20110502
CLK
. The multiplexer
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CLK