MAX503CAG+T Maxim Integrated Products, MAX503CAG+T Datasheet - Page 13

• Manufacturer Part Number: MAX503CAG+T
• Description: IC DAC 10BIT 5V LP 24-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX503CAG+T

• Settling Time: 25µs
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 640mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5 shows the circuit configuration for a 4-bit µP
application. Figure 6 shows the corresponding timing
sequence. The 4 low bits (S0, S1, D0, D1) are connect-
ed in parallel to the other 4 bits (D2–D5) and then to the
µP bus. Address lines A0 and A1 enable the input data
latches for the high, middle, or low data nibbles. The µP
sends chip select (CS) and write (WR) signals to latch
in each of three nibbles in three cycles when the data is
valid.
Figure 7 shows a typical interface to an 8-bit or a 16-bit
µP. Connect 8 data bits from the data bus to pins S0,
S1, and D0–D5 on the MAX503. With LDAC held high,
the user can load NBH or NBL + NBM in any order.
Figure 8a shows the corresponding timing sequence.
For fastest throughput, use Figure 8b’s sequence.
Address lines A0 and A1 are tied together and the DAC
is loaded in 2 cycles as 8 + 4. In this scheme, with
LDAC held low, the DAC latch is transparent. Always
load NBL and NBM first, followed by NBH.
Figure 8b. 8-Bit and 16-Bit µP Timing Sequence with LDAC = 0
Figure 9. Unipolar Configuration (0V to +2.048V Output)
33µF
NBL & NBM
REFIN
REFOUT
AGND
DGND
REFGND
______________________________________________________________________________________
LDAC = 0 (DAC LATCH IS TRANSPARENT)
NBH
WR
CS
0V TO -5V
MAX503
V
+5V
V
SS
DD
ROFS
VOUT
RFB
G = 1
5V, Low-Power, Parallel-Input,
V
OUT
A0 = A1 = 0
Voltage-Output, 10-Bit DAC
LDAC is asynchronous with respect to WR. If LDAC is
brought low before or at the same time WR goes high,
LDAC must remain low for at least 50ns to ensure the
correct data is latched. Data is latched into DAC regis-
ters on LDAC’s rising edge.
The MAX503 is configured for a 0V to V
output range by connecting ROFS and RFB to VOUT
(Figure 9). The converter operates from either single or
dual supplies in this configuration. See Table 3 for the
DAC-latch contents (input) vs. the analog VOUT (output).
In this range, 1LSB = V
A 0V to 2V
necting ROFS to AGND and RFB to VOUT (Figure 10).
Table 4 shows the DAC-latch contents vs. VOUT. The
MAX503 operates from either single or dual supplies in
this mode. In this range, 1LSB = (2)(V
(V
Figure 10. Unipolar Configuration (0V to +4.096V Output)
REFIN
A0 = A1 = 1
)(2
DAC UPDATE
REFIN
-9
33µF
).
unipolar output range is set up by con-
REFIN
REFOUT
ROFS
AGND
DGND
REFGND
REFIN
0V TO -5V
MAX503
Unipolar Configuration
V
+5V
V
SS
DD
(2
-10
VOUT
).
RFB
REFIN
G = 2
REFIN
)(2
V
OUT
unipolar
-10
) =
13