72T36125L5BBI Integrated Device Technology (Idt), 72T36125L5BBI Datasheet - Page 12

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72T36125L5BBI

Manufacturer Part Number
72T36125L5BBI
Description
FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 256K x 36 240-Pin BGA
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 72T36125L5BBI

Package
240BGA
Configuration
Dual
Bus Directional
Uni-Directional
Density
9 Mb
Organization
256Kx36
Data Bus Width
36 Bit
Timing Type
Asynchronous|Synchronous
Expansion Type
Depth|Width
Typical Operating Supply Voltage
2.5 V
Operating Temperature
-40 to 85 °C
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
A
CLK
CLKH
DS
DH
ENH
LDS
LDH
WCSH
S
SCKH
SDH
SENH
RS
HRSS
RSR
CLKL
ENS
WCSS
SCLK
SCKL
SDS
SENS
RSS
RSF
WFF
REF
PAFS
PAES
ERCLK
CLKEN
RCSLZ
RCSHZ
SKEW1
SKEW2
Clock Cycle Frequency (Synchronous)
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Load Setup Time
Load Hold Time
WCS setup time
WCS hold time
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
Reset Pulse Width
Reset Setup Time
HSTL Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to Synchronous Programmable Almost-Full Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
RCLK to Echo RCLK output
RCLK to Echo REN output
RCLK to Active from High-Z
RCLK to High-Z
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
CC
= 2.5V ± 5%, T
(3)
(2)
Parameter
A
= 0°C to +70°C;Industrial: V
(3)
CC
= 2.5V ± 5%, T
IDT72T36105L4-4
IDT72T36115L4-4
IDT72T36125L4-4
(1)
IDT72T3645L4-4
IDT72T3655L4-4
IDT72T3665L4-4
IDT72T3675L4-4
IDT72T3685L4-4
IDT72T3695L4-4
Min.
4.44
Commercial
100
0.6
2.0
2.0
1.2
0.5
1.2
0.5
1.2
0.5
1.2
0.5
3.5
45
45
15
30
15
10
5
5
5
4
4
— SYNCHRONOUS TIMING
12
Max.
225
3.4
3.4
3.4
3.4
3.4
3.8
3.4
3.4
3.4
10
10
A
= -40°C to +85°C)
IDT72T36105L5
IDT72T36115L5
IDT72T36125L5
IDT72T3645L5
IDT72T3655L5
IDT72T3665L5
IDT72T3675L5
IDT72T3685L5
IDT72T3695L5
Com’l & Ind’l
Min.
100
0.6
2.3
2.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
45
45
15
30
15
10
5
5
5
5
4
4
5
Max.
200
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
10
12
4
IDT72T36105L6-7 IDT72T36105L10
IDT72T36115L6-7 IDT72T36115L10
IDT72T36125L6-7 IDT72T36125L10
IDT72T3645L6-7
IDT72T3655L6-7
IDT72T3665L6-7
IDT72T3675L6-7
IDT72T3685L6-7
IDT72T3695L6-7
100
0.6
6.7
2.8
2.8
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
Min.
45
45
15
30
15
10
5
5
5
4
5
6
COMMERCIAL AND INDUSTRIAL
Max.
Commercial
150
3.8
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
10
15
TEMPERATURE RANGES
100
Min.
0.6
4.5
4.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
10
45
45
15
30
15
10
5
5
5
4
7
8
FEBRUARY 4, 2009
100
Max.
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
10
15
5
MHz
MHz
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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