72T36125L5BBI Integrated Device Technology (Idt), 72T36125L5BBI Datasheet - Page 24

• Manufacturer Part Number: 72T36125L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 256K x 36 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T36125L5BBI

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 9 Mb
• Organization: 256Kx36
• Data Bus Width: 36 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

SIGNAL DESCRIPTION
INPUTS:
DATA IN (D
(D
CONTROLS:
MASTER RESET ( MRS )
state. This operation sets the internal read and write pointers to the first location
of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
during the Master Reset cycle.
Reset is required after power up, before a write operation can take place. MRS
is asynchronous.
PARTIAL RESET (PRS)
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH,
and HF goes HIGH.
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then OR will go HIGH, and IR will go LOW.
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes. PRS is asynchronous.
operation, when reprogramming programmable flag offset settings may not be
convenient.
ASYNCHRONOUS WRITE (ASYW)
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronous operation of the write port will be selected. During Asynchro-
nous operation of the write port the WCLK input becomes WR input, this is the
Asynchronous write strobe input. A rising edge on WR will write data present
on the Dn inputs into the FIFO. (WEN must be tied LOW when using the write
port in Asynchronous mode).
(FF) operates in an asynchronous manner, that is, the full flag will be updated
based in both a write operation and read operation. Note, if Asynchronous
mode is selected, FWFT is not permissable. Refer to Figures 30, 31, 34 and
35 for relevant timing and operational waveforms.
ASYNCHRONOUS READ (ASYR)
mode of operation. If during a Master Reset the ASYR input is LOW, then
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
0
Data inputs for 36-bit wide data (D
A Master Reset is accomplished whenever the MRS input is taken to a LOW
All control settings such as OW, IW, BM, BE, RM, PFM and IP are defined
During a Master Reset, the output register is initialized to all zeroes. A Master
See Figure 9, Master Reset Timing, for the relevant timing diagram.
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
Whichever mode is active at the time of Partial Reset, IDT Standard mode
Following Partial Reset, all values held in the offset registers remain
A Partial Reset is useful for resetting the device during the course of
See Figure 10, Partial Reset Timing, for the relevant timing diagram.
The write port can be configured for either Synchronous or Asynchronous
When the write port is configured for Asynchronous operation the full flag
The read port can be configured for either Synchronous or Asynchronous
- D
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
17
) or data inputs for 9-bit wide data (D
0
- D
n
)
0
- D
35
), data inputs for 18-bit wide data
0
- D
8
).
24
Asynchronous operation of the read port will be selected. During Asynchro-
nous operation of the read port the RCLK input becomes RD input, this is the
Asynchronous read strobe input. A rising edge on RD will read data from the
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operation of the read port).
asynchronous manner. (RCS, provides three-state control of the read port in
Synchronous mode).
must be operating on IDT standard mode, FWFT mode is not permissible if the
read port is Asynchronous. The Empty Flag (EF) operates in an Asynchronous
manner, that is, the empty flag will be updated based on both a read operation
and a write operation. Refer to figures 32, 33, 34 and 35 for relevant timing and
operational waveforms.
RETRANSMIT (RT)
together they provide a means by which data previously read out of the FIFO
can be reread any number of times. If retransmit operation has been selected
(i.e. the MARK input is HIGH), a rising edge on RCLK while RT is LOW will reset
the read pointer back to the memory location set by the user via the MARK input.
LOW for the time that RT is held LOW. RT can be held LOW for any number
of RCLK cycles, the read pointer being reset to the marked location. The next
rising edge of RCLK after RT has returned HIGH, will cause EF to go HIGH,
allowing read operations to be performed on the FIFO. The next read operation
will access data from the ‘marked’ memory location.
pointer returning to the ‘marked’ location. See Figure 18, Retransmit from Mark
(IDT Standard mode) for the relevant timing diagram.
for the time that RT is held LOW. RT can be held LOW for any number of RCLK
cycles, the read pointer being reset to the ‘marked’ location. The next RCLK
rising edge after RT has returned HIGH, will cause OR to go LOW and due to
FWFT operation, the contents of the marked memory location will be loaded onto
the output register, a read operation being required for all subsequent data
reads.
pointer returning to the ‘marked’ location. See Figure 19, Retransmit from Mark
(FWFT mode) for the relevant timing diagram.
MARK
rising edge while MARK is HIGH will mark the memory location of the data
currently present on the output register, the device will also be placed into
retransmit mode. Note, for the IDT72T3645/72T3655/72T3665/72T3675/
72T3685/72T3695 there must be a minimum of 32 bytes of data between the
write pointer and read pointer when the MARK is asserted. For the IDT72T36105/
72T36115 there must be a minimum of 128 bytes, for the IDT72T36125 a
minimum of 256 bytes. Remember, 4 (x9) bytes = 2 (x18) words = 1 (x36) word.
Also, once the MARK is set, the write pointer will not increment past the “marked”
location until the MARK is deasserted. This prevents “overwriting” of retransmit
data.
mode, a falling edge of RCLK while MARK is LOW will take the device out of
retransmit mode and into normal mode. Any number of MARK locations can be
set during FIFO operation, only the last marked location taking effect. Once a
mark location has been set the write pointer cannot be incremented past this
The OE input provides three-state control of the Qn output bus, in an
When the read port is configured for Asynchronous operation the device
The Retransmit (RT) input is used in conjunction with the MARK input,
If IDT standard mode has been selected the EF flag will go LOW and remain
Subsequent retransmit operations may be performed, each time the read
If FWFT mode has been selected the OR flag will go HIGH and remain HIGH
Subsequent retransmit operations may be performed each time the read
The MARK input is used to select Retransmit mode of operation. An RCLK
The MARK input must remain HIGH during the whole period of retransmit
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 4, 2009