LFEC3E-3F256I Lattice, LFEC3E-3F256I Datasheet - Page 136
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-3F256I
Manufacturer Part Number
LFEC3E-3F256I
Description
FPGA LatticeEC Family 3100 Cells 340MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-3F256I
Package
256FBGA
Family Name
LatticeEC
Device Logic Units
3100
Maximum Internal Frequency
340 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
160
Ram Bits
56320
In System Programmability
Yes
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3F256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
Number
GND
GND
GND
GND
GND
M26
M22
M23
M25
M24
M21
Ball
U21
R23
R25
R24
R26
P26
R21
R22
P25
P24
P23
P22
N26
N21
P21
N23
N22
N25
N24
K26
T21
T25
T26
T22
T23
T24
L26
L21
L22
L23
L25
Function
PR36B
PR36A
PR35B
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
PR31A
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR18B
PR18A
PR17B
GND3
GND3
GND3
GND2
GND2
Ball
LFEC20/LFECP20
Bank LVDS
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Dual Function
PCLKC2_0
PCLKT2_0
RDQS36
RDQS28
RDQS19
4-70
Number
GND
GND
GND
GND
GND
M26
M22
M23
M25
M24
M21
Ball
U21
T21
T25
T26
T22
T23
T24
R23
R25
R24
R26
P26
R21
R22
P25
P24
P23
P22
N26
N21
P21
N23
N22
N25
N24
K26
L26
L21
L22
L23
L25
Function
PR48B
PR48A
PR47B
PR47A
PR46B
PR46A
PR45B
PR45A
PR44B
PR44A
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
PR40B
PR40A
PR39B
PR39A
PR38B
PR38A
PR37B
PR37A
PR36B
PR36A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
PR31A
PR30B
PR30A
PR29B
GND3
GND3
GND3
GND2
GND2
Ball
LatticeECP/EC Family Data Sheet
LFECP/EC33
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
LVDS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Pinout Information
PCLKC2_0
PCLKT2_0
Function
RDQS48
RDQS40
RDQS31
Dual
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