LFEC3E-3F256I Lattice, LFEC3E-3F256I Datasheet - Page 68
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LFEC3E-3F256I
Manufacturer Part Number
LFEC3E-3F256I
Description
FPGA LatticeEC Family 3100 Cells 340MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-3F256I
Package
256FBGA
Family Name
LatticeEC
Device Logic Units
3100
Maximum Internal Frequency
340 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
160
Ram Bits
56320
In System Programmability
Yes
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3F256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Signal Descriptions (Cont.)
TDI
TDO
V
Configuration Pads (used during sysCONFIG)
CFG[2:0]
INITN
PROGRAMN
DONE
CCLK
BUSY/SISPI
CSN
CS1N
WRITEN
D[7:0]/SPID[0:7]
DOUT/CSON
DI/CSSPIN
CCJ
Signal Name
I/O
I/O
I/O
I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
I/O Read control command in SPI3 or SPIX mode.
I/O sysCONFIG Port Data I/O.
I/O
—
O
O
I
I
I
I
I
I
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
Output pin. Test Data out pin used to shift data out of device using 1149.1.
V
Mode pins used to specify configuration modes values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
Write Data on Parallel port (Active low).
Output for serial configuration data (rising edge of CCLK) when using
sysCONFIG port.
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. Output when used in
SPI/SPIX modes.
CCJ
- The power supply pin for JTAG Test Access Port.
4-2
LatticeECP/EC Family Data Sheet
Description
Pinout Information
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