K6R4016V1D-UI10T00 SAMSUNG, K6R4016V1D-UI10T00 Datasheet - Page 9

• Manufacturer Part Number: K6R4016V1D-UI10T00
• Manufacturer: SAMSUNG

K6R4016V1D
TIMING WAVEFORM OF WRITE CYCLE(4)
TIMING WAVEFORM OF WRITE CYCLE(3)
Address
CS
UB, LB
WE
Data in
Data out
Data in
Data out
Address
CS
UB, LB
WE
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE
3. t
4. t
5. t
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
going low ; A write ends at the earliest transition CS going high or WE going high. t
to the end of write.
CW
AS
WR
of the output must not . be applied because bus contention can occur.
applied.
is measured from the address valid to the beginning of write.
is measured from the later of CS going low to end of write.
is measured from the end of write to the address change. t
High-Z
High-Z
High-Z
High-Z
t
AS(4)
t
AS(4)
(UB, LB Controlled)
(CS=Controlled)
t
LZ
t
BLZ
PRELIMPreliminaryPPPPPPPPPINARY
- 9 -
t
WHZ(6)
t
WHZ(6)
t
AW
t
AW
t
CW(3)
t
t
CW(3)
WC
t
t
BW
BW
t
WR
WC
t
WP(2)
t
WP(2)
applied in case a write ends as CS or WE going high.
t
DW
Valid Data
t
Valid Data
DW
WP
t
WR(5)
is measured from the beginning of write
t
DH
t
t
WR(5)
DH
High-Z(8)
High-Z(8)
CMOS SRAM
High-Z
Mar. 2004
Rev 4.0