MAX5134AGUE+ Maxim Integrated Products, MAX5134AGUE+ Datasheet - Page 11

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MAX5134AGUE+

Manufacturer Part Number
MAX5134AGUE+
Description
IC DAC 16BIT QUAD 16-TSSOP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX5134AGUE+

Settling Time
5µs
Number Of Bits
16
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
4
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
457mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX5134–MAX5137 digital inputs are double
buffered. Depending on the command issued through the
serial interface, the input register(s) can be loaded without
affecting the DAC register(s) using the write command. To
update the DAC registers, either pulse the LDAC input low
to synchronously update all DAC outputs, or use the soft-
ware LDAC command. Use the writethrough commands
(see Table 1) to update the DAC outputs immediately after
the data is received. Only use the writethrough command
to update the DAC output immediately.
The MAX5134/MAX5136 DAC code is unipolar binary
with V
MAX5137 DAC code is unipolar binary with V
(code/4096) x V
commands.
Connect the MAX5134–MAX5137 DVDD supply to the
supply of the host DSP or microprocessor. The AVDD
supply may be set to any voltage within the operating
Figure 2. Connections for MICROWIRE
Figure 4. READY Timing
READY 1
READY 2
READY 3
*THE READY-TO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICES
*BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
SCLK
DIN
OUT_
CS
= (code/65,536) x V
MAX5134–
MAX5137
1
REF
2
______________________________________________________________________________________
READY*
. See Table 1 for the serial interface
3
SCLK
DIN
CS
4
SLAVE 1 DATA
20
SO
SK
SI*
I/O
21
REF
22
MICROWIRE
PORT
. The MAX5135/
16-/12-Bit, Voltage-Output DACs
23 24
1
OUT_
2
3
Pin-/Software-Compatible,
=
4
SLAVE 2 DATA
5
range of 2.7V to 5.25V, but must be greater than or
equal to the DVDD supply.
Write to the MAX5134–MAX5137 using the following
sequence:
1) Drive CS low, enabling the shift register.
2) Clock 24 bits of data into DIN (C7 first and D0 last),
3) After clocking in the last data bit, drive CS high. CS
Figure 1 shows a write operation for the transmission of
24 bits. If CS is driven high at any point prior to receiving
24 bits, the transmission is discarded.
Figure 3. Connections for SPI/QSPI
observing the specified setup and hold times. Bits
D15–D0 are the data bits that are written to the
internal register.
must remain high for 33ns before the next transmis-
sion is started.
21
*THE READY-TO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICES BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
22
23 24
MAX5134–
MAX5137
1
READY*
SCLK
2
DIN
CS
3
4
Writing to the Devices
SLAVE 3 DATA
5
MOSI
MISO*
SCK
I/O
21
SPI/QSPI
+5V
PORT
SS
22
23 24
11

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