MT9075BP1 Zarlink, MT9075BP1 Datasheet - Page 5

• Manufacturer Part Number: MT9075BP1
• Description: PB FREE E1 SINGLE CHIP TRANSCEIVER
• Manufacturer: Zarlink

Pin Description (continued)
PLCC MQFP
13 -
21 -
26 -
12
16
17
18
19
20
24
25
30
31
32
33
34
35
36
37
38
39
40
41
Pin #
8-11
86-
94-
99,
85
89
90
91
92
93
97
98
12
13
14
15
16
17
18
19
20
21
22
RxDLCLK Receive Data Link Clock (Output). A gapped clock signal derived from a 2.048 Mbit/s
GNDARx Receive Analog Ground (Input). Analog ground for the LIU receiver.
INT/MOT Intel/Motorola Mode Selection (Input). A high on this pin configures the processor
VDDARx Receive Analog Power Supply (Input). Analog supply for the LIU receiver (+5V ± 5%).
R/W/WR Read/Write/Write Strobe (Input).
D0 - D3 Data 0 to Data 3 (Three-state I/O). These signals combined with D4-D7 form the
D4 - D7 Data 4 to Data 7 (Three-state I/O). These signals combined with D0-D3 form the
RRING
Name
AC0 -
RxDL
TxMF
RTIP
VDD
VDD
VSS
AC4
VSS
IRQ
IC
IC
IC
Interrupt Request (Output). A low on this output pin indicates that an interrupt request
is presented. IRQ is an open drain output that should be connected to V
up resistor. An active low CS signal is not required for this pin to function.
bidirectional data bus of the microprocessor interface (D0 is the least significant bit).
Negative Power Supply (Input). Digital ground.
Internal Connection. Tie to V
interface for the Intel parallel non-multiplexed bus type. A low configures the processor
interface for the Motorola parallel non-multiplexed type.
Positive Power Supply (Input). Digital supply (+5V ± 5%).
bidirectional data bus of the microprocessor interface (D7 is the most significant bit).
In Motorola mode (R/W), this input controls the direction of the data bus D[0:7] during
a microprocessor access. When R/W is high, the parallel processor is reading data
from the MT9075B. When low, the microprocessor is writing data to the MT9075B.
For Intel mode (WR), this active low write strobe configures the data bus lines as
output.
Address/Control 0 to 4 (Inputs). Address and control inputs for the microprocessor
interface. AC0 is the least significant input.
Receive TIP and RING (Inputs). Differential inputs for the receive line signal - must be
transformer coupled (See Figure 4).
Positive Power Supply (Input). Digital supply (+5V ± 5%).
Negative Power Supply (Input). Digital ground.
Internal Connection. Must be left open for normal operation.
Internal Connection. Must be left open for normal operation.
clock, available for an external device to clock in RxDL data (at 4, 8, 12, 16 or 20 kHz) on
the rising edge.
Receive Data Link (Output). A 2.048 Mbit/s data stream containing received line data
after HDB3 decoding. This data is clocked out with the rising edge of E2o.
Transmit Multiframe Boundary (Input). An active low input used to set the transmit
multiframe boundary (CAS or CRC multiframe). The MT9075B will generate its own
multiframe if this pin is held high. This input is usually pulled high for most applications.
Zarlink Semiconductor Inc.
MT9075B
SS
5
(Ground) for normal operation.
Description
DD
through a pull-
Data Sheet