MT9075BP1 Zarlink, MT9075BP1 Datasheet - Page 80
MT9075BP1
Manufacturer Part Number
MT9075BP1
Description
PB FREE E1 SINGLE CHIP TRANSCEIVER
Manufacturer
Zarlink
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7 - 0
7 - 0
Bit
Bit
Crc7 - 0
Cnt7 - 0
Name
Name
(0000
0000)
Table 94 - Transmit Byte Count Register
Table 93 - Receive CRC LSB Register
The LSB byte of the CRC received from the transmitter. These bits are as
the transmitter sent them; that is, most significant bit first and inverted.
This register is updated at the end of each received packet and therefore
should be read when end of packet is detected.
The Transmit Byte Count Register. It is used to indicate the length of the
packet about to be transmitted. When this register reaches the count of
one, the next write to the Tx FIFO will be tagged as an end of packet byte.
The counter decrements at the end of the write to the Tx FIFO. If the Cycle
bit of Control Register 2 is set high, the counter will cycle through the
programmed value continuously.
(Pages 0BH & 0CH, Address 19H)
(Pages B & C, Address 1AH)
Zarlink Semiconductor Inc.
MT9075B
80
Functional Description
Functional Description
Data Sheet
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