MAX5735BUTN+T Maxim Integrated Products, MAX5735BUTN+T Datasheet - Page 17

• Manufacturer Part Number: MAX5735BUTN+T
• Description: IC DAC 16BIT 32CHAN SER 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5735BUTN+T

• Settling Time: 20µs
• Number Of Bits: 16
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 32
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 2.5W
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: The offset DAC of every device can be pro-
grammed with any of the four output voltage ranges.
However, the specifications in the Electrical
Characteristics table are only guaranteed (production
tested) for the offset code associated with each partic-
ular part number. For example, the MAX5734 specifica-
tions are only valid with the MAX5734 offset- DAC code
shown in Table 1.
The offset DAC is summed with GS (Figure 1). The offset
DAC can also cancel the offset of the output buffers.
Any change in the offset DAC affects all 32 DACs.
The offset DAC is also configured identically to the
other 32 DACs with an input and DAC register. Write to
the offset DAC through the serial interface by using
control bits C2, C1, and C0 = 001 followed by the data
bits D15–D0. The CLR command affects the offset DAC
as well as the other DACs.
The data format for the offset DAC codes are: control bits
C2, C1, and C0 = 011, address bits A5–A0 = 100000, 7
don’t-care bits, and 16 data bits as shown in Table 2.
All DAC outputs are internally buffered. The internal
buffers provide gain, improved load regulation, and tran-
sition glitch suppression for the DAC outputs. The output
buffers slew at 1V/µs and can drive 10kΩ in parallel with
100pF. The output buffers are powered by AV
V
voltage range of the device.
Table 1. Offset DAC Codes
Note: For the MAX5732, the maximum code for the offset DAC is 16384. For the MAX5733/MAX5734/MAX5735, the maximum code
for the offset DAC is 40000.
Figure 3. LDAC Timing
SS
PART NUMBER
. AV
MAX5732
MAX5733
MAX5734
MAX5735
CC
LDAC
OUT_
and V
______________________________________________________________________________________
D15
SS
0
0
0
1
Output Amplifiers (OUT0–OUT31)
determine the maximum output
D14
0
0
1
0
D13
32-Channel, 16-Bit, Voltage-Output
0
0
0
0
D12
0
0
0
0
D11
0
0
0
0
t
LDAC
CC
D10
0
0
0
0
DACs with Serial Interface
and
D9
0
0
0
0
The input code, the voltage reference, the offset DAC
output, the voltage on GS, and the gain of the output
amplifier determine the output voltage. Calculate V
as follows:
where GAIN = 5/3 for the MAX5732, or GAIN = 10/3 for
the MAX5733/MAX5734/MAX5735.
The MAX5732–MAX5735 feature an active-low LDAC
logic input that allows the outputs OUT_ to update
asynchronously. Keep LDAC high during normal opera-
tion (when the device is controlled only through the ser-
ial interface). Drive LDAC low to simultaneously update
all DAC outputs with data from their respective input
registers. Figure 3 shows the LDAC timing with respect
to OUT_.
A software command can also activate the LDAC oper-
ation. To activate LDAC by software, set control bits
Table 2. Serial Data Format
V
CONTROL
OUT
D8
AND C0
0
0
0
0
C2, C1,
BITS
011
=
t
GAIN
S
D7
0
0
0
0
ADDRESS
×
D6
100000
A5–A0
0
0
0
0
V
BITS
REF
×
D5
0
0
0
0
(
DAC code
XXXXXXX
DON’T-
Load-DAC (LDAC) Input
CARE
2
BITS
D4
16
0
0
0
0
—
−
offset DAC code
D3
0
0
0
0
D2
0
0
0
0
DATA BITS
See table 1
±0.5 LSB
D15–D0
D1
0
0
0
0
)
+
V
OUT
GS
D0
0
0
0
0
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