AD5530BRU Analog Devices Inc, AD5530BRU Datasheet - Page 15

• Manufacturer Part Number: AD5530BRU
• Description: IC DAC 12BIT SRL IN/VOUT 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5530BRU

• Rohs Status: RoHS non-compliant
• Settling Time: 20µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 60mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP

MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5530/AD5531 is via a
serial bus that uses standard protocol compatible with micro-
controllers and DSP processors. The communications channel
is a 3-wire (minimum) interface consisting of a clock signal, a
data signal, and a synchronization signal. The AD5530/AD5531
requires a 16-bit data-word with data valid on the falling edge
of SCLK.
For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in or asynchronously
under the control of LDAC .
The contents of the DAC register can be read using the
readback function.
which is clocked out on SDO. Figure 23, Figure 24, and Figure 25
show these DACs interfacing with a simple 4-wire interface.
The serial interface of the AD5530/AD5531 can be operated
from a minimum of three wires.
AD5530/AD5531 TO ADSP-21xx
An interface between the AD5530/AD5531 and the ADSP-21xx
is shown in Figure 23. In the interface example shown, SPORT0
is used to transfer data to the DAC. The SPORT control register
should be configured as follows: internal clock operation,
alternate framing mode; active low framing signal.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the
the LDAC input could be tied permanently low and then the
update takes place automatically when TFS is taken high.
AD5530/AD5531 TO 8051 INTERFACE
A serial interface between the AD5530/AD5531 and the 8051 is
shown in Figure 24. TxD of the 8051 drives SCLK of the
AD5530/AD5531, while RxD drives the serial data line, SDIN.
P3.3 and P3.4 are bit-programmable pins on the serial port and
are used to drive SYNC and LDAC , respectively.
Figure 23. AD5530/AD5531 to ADSP-21xx Interface
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-2103
ADSP-2101/
RBEN is used to frame the readback data,
SCLK
TFS
FO
DT
1
LDAC pin via the DSP. Alternatively,
LDAC
SYNC
SDIN
SCLK
AD5531
AD5530/
1
Rev. B | Page 15 of 20
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user has to ensure that the data in the SBUF
register is arranged correctly because the DAC expects MSB first.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge. As a result no glue
logic is required between this DAC and microcontroller interface.
The 8051 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. As the DAC expects
a 16-bit word, P3.3 must be left low after the first 8 bits are
transferred. After the second byte has been transferred, the P3.3
line is taken high. The DAC can be updated using
P3.4 of the 8051.
AD5530/AD5531 TO MC68HC11 INTERFACE
Figure 25 shows an example of a serial interface between the
AD5530/AD5531 and the MC68HC11 microcontroller. SCK of
the MC68HC11 drives the SCLK of the DAC, and the MOSI
output drives the serial data lines, SDIN. SYNC is driven from
one of the port lines, in this case PC7.
The MC68HC11 is configured for master mode, MSTR = 1,
CPOL = 0, and CPHA = 1. When data is transferred to the part,
PC7 is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of SCK.
Eight falling clock edges occur in the transmit cycle, so to load the
required 16-bit word, PC7 is not brought high until the second
8-bit word has been transferred to the DAC input shift register.
Figure 25. AD5530/AD5531 to MC68HC11 Interface
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
80C51/80L51
Figure 24. AD5530/AD5531 to 8051 Interface
MC68HC11
MOSI
P3.4
P3.3
SCK
RxD
TxD
PC6
PC7
1
1
LDAC
SYNC
SDIN
SCLK
LDAC
SYNC
SDIN
SCLK
AD5531
AD5531
AD5530/
AD5530/
AD5530/AD5531
1
1
LDAC via