AD1866N Analog Devices Inc, AD1866N Datasheet - Page 8
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AD1866N
Manufacturer Part Number
AD1866N
Description
IC DAC AUDIO 16BIT DUAL 16-DIP
Manufacturer
Analog Devices Inc
Datasheet
1.AD1866RZ-REEL.pdf
(12 pages)
Specifications of AD1866N
Rohs Status
RoHS non-compliant
Number Of Bits
16
Data Interface
Serial
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
70mW
Operating Temperature
-35°C ~ 85°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Settling Time
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD1866NZ
Manufacturer:
AD
Quantity:
13 888
AD1866–Digital Circuit Considerations
INPUT DATA
The digital input port of the AD1866 employs five signals: Data
Left (DL), Data Right (DR), Latch Left (LL), Latch Right
(LR), and Clock (CLK). DL and DR are the serial inputs for
the left and right DACs, respectively. Input data bits are clocked
into the input register on the rising edge of CLK. The falling
edges of LL and LR cause the last 16 bits which were clocked
into the serial registers to be shifted into the DACs, thereby up-
dating the respective DAC outputs. For systems using only a
single latch signal, LL and LR may be connected together. For
systems using only one DATA signal, DR and DL may be con-
nected together. Data is transmitted to the AD1866 in a bit
stream composed of 16-bit words with a serial, twos comple-
ment, MSB first format. Left and right channels share the Clock
(CLK) signal.
Figure 9 illustrates the general signal requirements for data
transfer for the AD1866.
TIMING
Figure 10 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. The input pins of the AD1866 are both TTL and +5 V
CMOS compatible.
CLK
DL
DR
LL
LR
M
S
B
M
S
B
Figure 9. AD1866 Control Signals
–8–
The maximum clock rate of the AD1866 is specified to be at
least 13.5 MHz. This clock rate allows data transfer rates of 2 ,
4 , 8 , and 16 F
tions section of this data sheet contains additional guidelines for
using the AD1866.
DR/DL
LR/LL
CLK
Figure 10. AD1866 Input Signal Timing
>10ns
S
>30ns
(where F
>30ns
>67ns
S
>30ns
>40ns
>40ns
equals 44.1 kHz). The applica-
>10ns
>15ns
>40ns
L
S
B
L
S
B
REV. 0