AD9786BSVRL Analog Devices Inc, AD9786BSVRL Datasheet - Page 22

• Manufacturer Part Number: AD9786BSVRL
• Description: IC DAC 16BIT INTERPOL/SP 80TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9786BSVRL

• Number Of Bits: 16
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.25W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• For Use With: AD9786-EB - BOARD EVALUATION FOR AD9786
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Settling Time: -

AD9786
MODE CONTROL (VIA SERIAL PORT)
Table 11.
Address
COMMS
FILTER
DATA
MODULATE
RESERVED
DCLKCRC
CALMEMCK
MEMRDWR
MEMADDR
MEMDATA
DCRCSTAT
Table 12.
COMMS(00)
SDIODIR
DATADIR
SWRST
SLEEP
PDN
EXREF
Table 13.
FILTER(01)
INTERP[1:0]
ZSTUFF
HPFX8
HPFX4
HPFX2
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
Bit 7
SDIODIR
INTERP[1]
DATAFMT
CHANNEL
Reserved
DATAADJ[3]
CALSTAT
MEMADDR[7]
Bit
7
6
5
4
3
0
Bit
[7:6]
3
2
1
0
I
I
I
I
I
Direction
I
I
I
I
I
I
Direction
Bit 6
DATADIR
INTERP[0]
ONEPORT
HILBERT
Reserved
DATAADJ[2]
CALEN
MEMADDR[6]
Default
0
0
0
0
0
0
Default
00
0
0
0
0
Bit 5
SWRST
DCLKSTR
MODDUAL
Reserved
DATAADJ[1]
CALMEM[1]
XFERSTAT
MEMADDR[5]
MEMDATA[5]
Description
0: SDIO pin configured for input only during data transfer
1: SDIO configured for input or output during data transfer
0: Serial data uses MSB-first format
1: Serial data uses LSB-first format
1: Default all serial register bits, except Address 0x00 and Address 0x04
1: DAC output current off
1: All analog and digital circuitry, except serial interface, off
0: Internal band gap reference
1: External reference
Description
00: No interpolation
01: Interpolation 2×
10: Interpolation 4×
11: Interpolation 8×
1: Zero stuffing on
0: ×8 interpolation filter configured for low-pass
1: ×8 interpolation filter configured for high-pass
0: ×4 interpolation filter configured for low-pass
1: ×4 interpolation filter configured for high-pass
0: ×2 interpolation filter configured for low-pass
1: ×2 interpolation filter configured for high-pass
Rev. B | Page 22 of 56
Bit 4
SLEEP
DCLKPOL
SIDEBAND
Reserved
DATAADJ[0]
CALMEN[0]
XFEREN
MEMADDR[4]
MEMDATA[4]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 3
PDN
ZSTUFF
DCLKEXT
MOD[1]
Reserved
MODSYNC
SMEMWR
MEMADDR[3]
MEMDATA[3]
Bit 2
HPFX8
MOD[0]
Reserved
CALCKDIV[2]
SMEMRD
MEMADDR[2]
MEMDATA[2]
DCRCSTAT[2]
DCLKCRC
MODADJ[2]
CALCKDIV[2]
FMEMRD
MEMADDR[1]
MEMDATA[1]
DCRCSTAT[1]
Bit 1
HPFX4
IQPOL
Reserved
MODADJ[1]
Bit 0
EXREF
HPFX2
CRAYDIN
Reserved
MODADJ[0]
CALCKDIV[2]
UNCAL
MEMADDR[0]
MEMDATA[0]
DCRCSTAT[0]