AD9786-EB Analog Devices Inc, AD9786-EB Datasheet
AD9786-EB
Specifications of AD9786-EB
Related parts for AD9786-EB
AD9786-EB Summary of contents
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... On-chip voltage reference. The AD9786 includes a 1.20 V temperature-compensated band gap voltage reference. 8. Multichip synchronization. Multiple AD9786 DACs can be synchronized to a single master AD9786 to ease timing design requirements and optimize image reject transmit performance. FUNCTIONAL BLOCK DIAGRAM 2× 2× 2× ...
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... Digital Filter Specifications ........................................................... 26 Digital Interpolation Filter Coefficients.................................. 26 Clock/Data Timing .................................................................... 27 Real and Complex Signals......................................................... 32 Modulation Modes..................................................................... 33 Power Dissipation....................................................................... 38 Hilbert Transform Implementation......................................... 40 Operating the AD9786 Rev. F Evaluation Board ....................... 44 Power Supplies ............................................................................ 44 PECL Clock Driver .................................................................... 44 Data Inputs.................................................................................. 45 Serial Port .................................................................................... 45 Analog Output ............................................................................ 45 Outline Dimensions ....................................................................... 55 Ordering Guide .......................................................................... 55 ...
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... Change to Figure 51........................................................................29 Change to Figure 52........................................................................29 Change to Figure 53........................................................................30 Change to DATAADJUST Synchronization Section..................31 Changes to Power Dissipation Section.........................................40 Changes to Table 37 ........................................................................42 Changes to Data Inputs Section ....................................................46 Change to Figure 88........................................................................49 Replaced Figure 95..........................................................................55 Updated Outline Dimensions........................................................60 Changes to Ordering Guide...........................................................60 7/04—Revision 0: Initial Version Rev Page AD9786 ...
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... V p-p sine wave, CMOS, and LVPECL in single-ended or differential mode. Internal dividers generate the required data rate interface clocks. The AD9786 provides a differential current output, supporting single-ended or differential applications; it provides a nominal full-scale current from mA. The AD9786 is manufactured on an advanced, low cost, 0.25 μm CMOS process. Rev Page ...
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... V 1 μA 0.1 1. MΩ 200 kHz 0 ppm of FSR/°C ±4 ppm of FSR/°C ±30 ppm/°C 3.1 3.3 3 2.35 2.5 2.65 V 2.5 mA 2.35 2.5 2. 2.35 2.5 2.65 V 52.5 mA 3.1 3.3 3.5 V 5.3 μA 1.25 W –40 +85 °C /4 modulation, Hilbert off. AD9786 ...
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... AD9786 DYNAMIC SPECIFICATIONS AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2 MIN MAX coupled output; 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Minimum DAC Output Update Rate Maximum DAC Output Update Rate (f AC LINEARITY/BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist ( 100 MSPS ...
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... Data Hold Time to DACCLK Out in Master Mode (t 1 See the Clock/Data Timing section for setup and hold times in various timing modes. Min 1.6 –10 –10 0 0.75 0 −0 2.9 H Rev Page AD9786 = 20 mA, unless otherwise noted. OUTFS Typ Max Unit V 0 0.9 V +10 μA +10 μ 2. ...
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... AD9786 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter With Respect to AVDD1, AVDD2, AGND1, AGND2, DRVDD ACGND, ADGND, CLKGND, DGND ACVDD, ADVDD, AGND1, AGND2, CLKVDD, DVDD ACGND, ADGND, CLKGND, DGND AGND1, AGND2, AGND1, AGND2, ACGND, ADGND, ACGND, ADGND, CLKGND, DGND CLKGND, DGND REFIO, FSADJ ...
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... Pin configured for input of channel data rate or synchronizer clock. Internal clock synchronizer can be turned on or off with DCLKCRC (0x02[2]). 1 Pin configured for output of channel data rate or synchronizer clock. Clock Domain 2.5 V. Clock Domain 0 V. Rev Page AD9786 FSADJ 60 REFIO 59 RESET 58 CSB ...
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... AD9786 ANALOG Table 7. Analog Pin Function Descriptions Pin No. Mnemonic 59 REFIO 60 FSADJ 70, 71 IOUTB, IOUTA 61 DNC 62, 79 ADVDD 63, 78 ADGND 64, 77 ACVDD 65, 76 ACGND 66, 75 AVDD2 67, 74 AGND2 68, 73 AVDD1 69, 72 AGND1 80 DNC DATA Table 8. Data Pin Function Descriptions Pin No. Mnemonic ...
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... Serial data output High impedance. SDIODIR CSB 0x00[7] Mode 1 X High impedance Serial data output Serial data input/output depending on Bit 7 of the serial instruction byte. Serial Interface Clock. Serial Interface Chip Select. Resets entire chip to default state. Rev Page AD9786 ...
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... AD9786 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normal- ized to full scale, associated with a 1 LSB change in digital input code ...
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... IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or jwt = lower frequency image near the second IF can be rejected. Rev Page AD9786 ...
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... AD9786 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2 MIN MAX coupled output; 50 Ω doubly terminated, unless otherwise noted. 120 100 –6dBFS 80 60 0dBFS FREQUENCY (MHz) Figure 3. SFDR vs. Frequency 200 MSPS, 1× Interpolation DATA 120 –3dBFS 100 –6dBFS ...
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... Figure 14. Third-Order IMD vs. Frequency, f Rev Page 0dBFS –3dBFS –6dBFS ANALOG OUTPUT FREQUENCY (MHz) = 100 MSPS, 4× Interpolation DATA 0dBFS –6dBFS –3dBFS ANALOG OUTPUT FREQUENCY (MHz MSPS, 8× Interpolation DATA –3dBFS 0dBFS –6dBFS (MHz) OUT = 160 MSPS, 1× Interpolation DATA AD9786 25 80 ...
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... AD9786 100 95 –3dBFS 0dBFS 100 F (MHz) OUT Figure 15. Third-Order IMD vs. Frequency, f DATA 100 95 –3dBFS 90 –6dBFS 0dBFS 100 120 F (MHz) OUT Figure 16. Third-Order IMD vs. Frequency, f DATA 100 95 0dBFS 90 85 –6dBFS –3dBFS 100 120 140 160 180 F (MHz) OUT Figure 17. Third-Order IMD vs. Frequency, f DATA – ...
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... Figure 24. Typical DNL F = 78MSPS, 1× INTERPOLATION DATA F = 78MSPS, 2× INTERPOLATION DATA ANALOG OUTPUT FREQUENCY (MHz) Figure 25. Noise Spectral Density vs. Analog Input Frequency MSPS DATA A = –3DBFS 0DBFS –6DBFS ANALOG OUTPUT FREQUENCY (MHz) Figure 26. Noise Spectral Density vs. Analog Input Frequency MSPS, 2x Interpolation DATA AD9786 65536 ...
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... AD9786 –150 –152 –154 A = –3dBFS IN –156 –158 A = 0dBFS IN –160 –162 A IN –164 –166 –168 –170 100 ANALOG OUTPUT FREQUENCY (MHz) Figure 27. Noise Spectral Density vs. Analog Input Frequency 156 MSPS, 2x Interpolation DATA –60 –65 –70 –3dBFS 0dBFS –75 –80 –6dBFS –85 –90 ...
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... Figure 35. ACLR for Four WCDMA Carriers Near 50 MHz 61.44 MSPS, 4× Interpolation DATA AD9786 dBm –20.48 –92.37 –93.18 –92.88 –92.35 ...
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... SCLK—Serial Clock. The serial clock pin is used to synchronize data to and from the AD9786 and to run the internal state machines. The maximum frequency of SCLK is 20 MHz. All data input to the AD9786 is registered on the rising edge of SCLK. All data is driven out of the AD9786 on the falling edge of SCLK. ...
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... DATADIR (0x00[6]). The default is MSB first. When this bit is set active high, the AD9786 serial port is in LSB-first format. That is, if the AD9786 is in LSB-first mode, the instruction byte must be written from least significant bit to most significant bit. Multibyte data transfers in MSB-first format can be completed by writing an instruction byte that includes the register address of the most significant byte ...
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... AD9786 MODE CONTROL (VIA SERIAL PORT) Table 11. Address Bit 7 Bit 6 COMMS 00 SDIODIR DATADIR FILTER 01 INTERP[1] INTERP[0] DATA 02 DATAFMT ONEPORT MODULATE 03 CHANNEL HILBERT RESERVED 04 Reserved Reserved DCLKCRC 05 DATAADJ[3] DATAADJ[ CALMEMCK 0E MEMRDWR 0F CALSTAT CALEN MEMADDR 10 MEMADDR[7] MEMADDR[6] MEMDATA 11 DCRCSTAT 12 Table 12. COMMS(00) Bit Direction ...
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... Modulator uses both I and Q channels 0 0: With MODDUAL on, upper sideband rejected 1: With MODDUAL on, lower sideband rejected 00 00: No modulation 01 modulation S 10 modulation S 11 modulation S Rev Page AD9786 I channel processing routed to DAC Q channel processing routed to DAC Modulator real output routed to DAC Modulator imaginary output routed to DAC ...
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... AD9786 Table 16. DCLKCRC(05) Bit Direction DATAADJ[3:0] [7:4] I MODSYNC 3 I MODADJ[2:0] [2:0] I Table 17. VERSION(0D) Bit Direction VERSION[3:0] [3:0] O Table 18. CALMEMCK(OE) Bit Direction CALMEM [5:4] O CALCKDIV[2:0] [2:0] I Table 19. MEMRDWR(OF) Bit Direction CALSTAT 7 O CALEN 6 I XFERSTAT 5 O XFEREN 4 I SMEMWR 3 I SMEMRD 2 I FMEMRD ...
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... With DATACLK CRC on, lock has been achieved at least once 0 0: With DATACLK CRC on, system is currently not locked 1: With DATACLK CRC on, system is currently locked 0 0: With DATACLK CRC on, system is currently locked 1: With DATACLK CRC on, system lost lock due to jitter Rev Page AD9786 ...
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... AD9786 DIGITAL FILTER SPECIFICATIONS DIGITAL INTERPOLATION FILTER COEFFICIENTS Table 23. Stage 1 Interpolation Filter Coefficients Lower Coefficient Upper Coefficient H(1) H(43) H(2) H(42) H(3) H(41) H(4) H(40) H(5) H(39) H(6) H(38) H(7) H(37) H(8) H(36) H(9) H(35) H(10) H(34) H(11) H(33) H(12) H(32) ...
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... DACCLK and DATACLK. The DCLKPOL bit (Register 0x02, Bit 4) allows the data to be latched into the AD9786 upon either the rising or falling edge of DACCLK. With DCLKPOL = 0, the data is latched in upon the falling edge of DACCLK, as shown in Figure 44. With DCLKPOL = 1, as shown in Figure 45, data is latched in upon the rising edge of DACCLK ...
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... AD9786. A clock running at the DAC sample rate, referred to as DACCLK, must be applied to the differential inputs (Pin 5 and Pin 6) of the AD9786. As described previously, a clock at the input sample rate must also be applied to Pin 31 (DATACLK). An internal DLL synchronizes the two applied clocks. The timing relationships between the input data, DATACLK, and DACCLK are given in Figure 49 and Figure 50 ...
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... If setup and hold is violated, DCLKPOL can be switched. The effect of switching the state of DCLKPOL is that the latching edge is moved by one, two, or four DACCLK cycles if the AD9786 is in 2×, 4×, or 8× interpolation modes, respectively. Note that in this mode, the DATAADJ bits have no effect. ...
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... DATAADJ are diminished to +1 cycle to –2 cycles. Figure 54, Figure 55, and Figure 56 show the alignment for the latching edge of DACCLK with 4× interpolation and different settings for DATAADJ. In Figure 54, the AD9786 is in DATACLK master mode. DATAADJ is set to 0000, with DCLKPOL set that the latching edge of DACCLK is immediately before the rising edge of DATACLK ...
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... Interpolation filter responses are achieved by cascading individual digital filter banks, whose filter coefficients are given in Table 23, Table 24, and Table 25. Filter responses are shown in Figure 57, which shows the interpolation filters of the AD9786 under different interpolation rates, normalized to the input data rate, f ...
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... Q complex signal component— represents a signal on the imaginary plane with mirror asymmetry about dc. The AD9786 has two channels of interpolation filters, allowing both I and Q components to be shaped by the same filter transfer function. The interpolation filter’s frequency response is a real transfer function ...
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... Either channel of the AD9786 interpolation filter channels can be routed to the DAC and modulated. In single-channel operation, the input data can be modulated by a real sinusoid; the input data and the modulating sinusoid contain both positive and negative frequency components. A double side- band output results when modulating two real signals. At the DAC output, the positive and negative frequency components add in phase, resulting in constructive signal summation ...
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... AD9786 0 –50 –100 –150 –8 –6 –4 0 –50 –100 –150 –8 –6 –4 0 –50 –100 –150 –8 –6 –4 0 –50 –100 –150 –8 –6 –4 FILTERED INTERPOLATION IMAGES f /8 MODULATION S Figure 59. Double Sideband Modulation – – – – Figure 60. Real Modulation by f ...
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... Figure 62. Real Modulation by f – – – – Under All Interpolation Modes DAC – – – – Under All Interpolation Modes DAC Rev Page AD9786 NO INTERPOLATION INTERP[ INTERP[ MOD[ MOD[ SIN ×2 INTERPOLATION INTERP[ INTERP[ MOD[ MOD[ SIN ×4 INTERPOLATION INTERP[ INTERP[ MOD[ MOD[ SIN × ...
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... AD9786 Table 33. Dual-Channel Complex Modulation MODDUAL CHANNEL dual-channel mode, the two channels can be modulated by a complex signal, with either the real or imaginary modulation result directed to the DAC. Assume initially Figure 63, that the complex modulating signal is defined for a positive frequency only. This causes the output spectrum to be trans- lated in frequency by the modulation factor only. No additional sidebands are created as a result of the modulation process ...
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... Under All Interpolation Modes DAC – – – Under All Interpolation Modes DAC – – – Under All Interpolation Modes DAC Rev Page AD9786 ×2 INTERPOLATION INTERP[ INTERP[ MOD[ MOD[ SIN ×4 INTERPOLATION INTERP[ INTERP[ MOD[ MOD[ SIN ×8 INTERPOLATION INTERP[ INTERP[ MOD[ MOD[ ...
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... The current needed for the 3.3 V analog supplies, AVDD1 and AVDD2, is consistent across speed and varying modes of the AD9786. Nominally, the current for AVDD1 across all speeds and modes, whereas the current for AVDD2 is 20 mA. The current for the 2.5 V analog supplies and the digital supplies varies depending on speed and mode of operation ...
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... A/2 Figure 71. Negative Frequency Image Rejection In Figure 71, Figure X represents a complex signal typically found in the AD9786 signal path. Figure Y is identical to Figure X, but it is shifted by π/2. The phase shifting in the AD9786 occurs because the digital LO driving the digital quadrature modulator in the Hilbert transform path is phase shifted by π/2. ...
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... Figure 73. Effects of Hilbert Transform If the output of the AD9786 is used with a quadrature modulator, negative frequency images are cancelled without the need for a Hilbert transform. HILBERT TRANSFORM IMPLEMENTATION The Hilbert transform on the AD9786 is implemented as a 19-coefficient FIR. The coefficients are given in Table 36. ...
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... Q Figure 77. AD9786 Driving Quadrature Modulator The AD9786 can be configured to drive a quadrature modulator Figure 77. When two AD9786s are used with one AD9786 producing the real output, the second AD9786 produces the imaginary output. By configuring the AD9786 as a complex modulator coupled to a quadrature modulator, IF image rejection is possible ...
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... AD9786 Master/Slave, Modulator/DATACLK Master Modes In applications where two or more AD9786s are used to synthe- size several digital data paths, it might be necessary to ensure that the digital inputs to each device are latched synchronously. In complex data processing applications, digital modulator phase alignment might be required between two AD9786s. To allow ...
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... MODADJ[2:0] 000 DAC CLOCK STATE MACHINE MODULATOR – COEFFICIENT STATE MACHINE CYCLE CLOCK Figure 84. Local Modulator Coefficient Synchronized with Offset 1111 – – – Figure 83. Digital Modulator State Machine Decode 010 – –1 Rev Page 0001 + – – 101 –1 AD9786 ...
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... JP1, which is just to the left of the chip on the evaluation board. With the jumper set to the 3.3 V position, the DRVDD chip receives its power from VDD3IN. ACLKX Table 38. Power Supply Domains on AD9786 Rev. F Evaluation Board Evaluation Board Label/PS Domain on Chip DVDD CLKVDD ...
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... The input level should be 3.3 V. The data format is selectable through Register 0x02, Bit 7 (DATAFMT). With this bit set to a default 0, the AD9786 assumes that the input data is in twos complement format. With this bit set to 1, data should be input in offset binary format. ...
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... AD9786 Figure 87. Power Supply Distribution, Rev. F Evaluation Board Rev Page ...
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... ADTL1-12 Figure 88. AD9786 Local Circuitry, Rev. F Evaluation Board Rev Page AD9786 ...
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... AD9786 AX15 AX14 AX13 AX12 DATA-A AX15 2 1 AX14 4 3 AX13 6 5 AX12 8 7 AX11 10 9 AX10 12 11 AX09 14 13 AX08 16 15 AX07 18 17 AX06 20 19 AX05 22 21 AX04 24 23 AX03 26 25 AX02 28 27 AX01 30 29 AX00 RIBBON J1 AX07 AX06 AX05 AX04 Figure 89 ...
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... RP3 RP3 RP3 RP3 RP3 RP4 RP4 RP4 RP4 RP4 RP4 RP4 RP4 RP11 DNP JP25 JP24 AD9786 RP9 DNP 9 10 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 BD05 BD04 BD03 BD02 BD01 BD00 9 10 RP10 DNP ...
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... AD9786 DVDDS 4 PRE OPCLK_3 OPCLK 1 CLK CLR 15 74LCX112 DGND;8 U7 DVDDS;16 10 PRE CLK CLR 14 74LCX112 DGND;8 U7 DVDDS;16 SPCSB SPCLK SPSDI SPSDO R21 10kΩ C52 + C53 4.7μF 0.1μF 6.3V R50 U5 U5 9kΩ 74AC14 74AC14 R48 U5 U5 9kΩ 74AC14 74AC14 R45 ...
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... Figure 92. PCB Assembly, Primary Side, Rev. F Evaluation Board Figure 93. PCB Assembly, Secondary Side, Rev. F Evaluation Board Rev Page AD9786 ...
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... AD9786 Figure 94. PCB Assembly, Layer 1 Metal, Rev. F Evaluation Board Figure 95. PCB Assembly, Layer 6 Metal, Rev. F Evaluation Board Rev Page ...
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... Figure 96. PCB Assembly, Layer 2 Metal (Ground Plane),Rev. F Evaluation Board Figure 97. PCB Assembly, Layer 3 Metal (Power Plane),Rev. F Evaluation Board Rev Page AD9786 ...
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... AD9786 Figure 98. PCB Assembly, Layer 4 Metal (Power Plane), Rev. F Evaluation Board Figure 99. PCB Assembly, Layer 5 Metal (Ground Plane), Rev. F Evaluation Board Rev Page ...
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... VIEW A ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range AD9786BSV −40°C to +85°C AD9786BSVRL −40°C to +85°C 1 AD9786BSVZ −40°C to +85°C 1 AD9786BSVZRL −40°C to +85°C AD9786- Pb-free part. 14.20 14.00 SQ 12.20 13.80 1.20 12.00 SQ MAX 11. PIN 1 TOP VIEW ...
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... AD9786 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03152-0-10/05(B) Rev Page ...