ISL5629IN Intersil, ISL5629IN Datasheet - Page 11
![no-image](/images/manufacturer_photos/0/3/341/intersil_sml.jpg)
ISL5629IN
Manufacturer Part Number
ISL5629IN
Description
IC DAC DUAL 8BIT 3.3V 48-LQFP
Manufacturer
Intersil
Datasheet
1.ISL5629INZ.pdf
(12 pages)
Specifications of ISL5629IN
Number Of Bits
8
Data Interface
Parallel
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
274mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Settling Time
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Timing Diagram
R
R
ISL5629
ISL5629
EQ
EQ
AT EACH OUTPUT
= 0.5 x (R
= 0.5 x (R
AT EACH OUTPUT
FIGURE 6. OUTPUT LOADING FOR DATASHEET
FIGURE 7. ALTERNATIVE OUTPUT LOADING
D7-D0
LOAD
LOAD
I
CLK
OUT
FIGURE 8. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
OUTB
OUTB
OUTA
OUTA
// R
// R
DIFF
DIFF
MEASUREMENTS
R
LOAD SEEN BY THE TRANSFORMER
LOAD
R
)
// R
R
R
LOAD SEEN BY THE TRANSFORMER
DIFF
DIFF
LOAD
R
R
A
REPRESENTS THE
B
), WHERE R
A
11
REPRESENTS THE
t
SU
V
W
V
OUT
OUT
0
1:1
A
=R
= (2 x OUTA x R
= (2 x OUTA x R
B
t
PW1
t
HLD
t
PD
R
OUTPUT=W
R
LOAD
EQ
LOAD
EQ
t
)V
PW2
)V
t
SU
ISL5629
W
1
-1
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 8.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
t
HLD
t
PD
OUTPUT=W
t
SU
W
2
0
t
HLD
OUTPUT=W
W
1
3
50%