CY37256P160-125AXC Cypress Semiconductor Corp, CY37256P160-125AXC Datasheet - Page 29

IC CPLD 256 MACROCELL 160LQFP

CY37256P160-125AXC

Manufacturer Part Number
CY37256P160-125AXC
Description
IC CPLD 256 MACROCELL 160LQFP
Manufacturer
Cypress Semiconductor Corp
Series
Ultra37000™r

Specifications of CY37256P160-125AXC

Number Of Macrocells
256
Package / Case
160-LQFP
Programmable Type
In-System Reprogrammable™ (ISR™) CMOS
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of I /o
133
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Voltage
5V
Memory Type
CMOS
Number Of Product Terms Per Macro
16
Maximum Operating Frequency
125 MHz
Delay Time
10 ns
Number Of Programmable I/os
133
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Family Name
Ultra 37000
# Macrocells
256
Number Of Usable Gates
7700
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
16
# I/os (max)
133
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY3720 - ADAPTER SOCKET PTG
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1725
CY37256P160125AXC
CY37256P160125AXC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY37256P160-125AXC
Manufacturer:
CYPRESS
Quantity:
8 831
Part Number:
CY37256P160-125AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-03007 Rev. *E
Typical 3.3V Power Consumption (continued)
CY37192V
CY37256V
1 2 0
1 0 0
1 4 0
1 2 0
1 0 0
8 0
6 0
4 0
2 0
0
8 0
6 0
4 0
2 0
0
0
0
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
2 0
2 0
V
V
CC
CC
4 0
4 0
= 3.3V, T
= 3.3V, T
F r e q u e n c y ( M H z )
A
A
F r e q u e n c y ( M H z )
= Room Temperature
= Room Temperature
6 0
6 0
L o w P o w e r
L o w P o w e r
8 0
8 0
Ultra37000 CPLD Family
1 0 0
1 0 0
H ig h S p e e d
H ig h S p e e d
1 2 0
1 2 0
Page 29 of 64

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