EPM9320LC84-15 Altera, EPM9320LC84-15 Datasheet - Page 21
![IC MAX 9000 CPLD 320 84-PLCC](/photos/6/70/67059/544-84-plcc_sml.jpg)
EPM9320LC84-15
Manufacturer Part Number
EPM9320LC84-15
Description
IC MAX 9000 CPLD 320 84-PLCC
Manufacturer
Altera
Series
MAX® 9000r
Datasheet
1.EPM9320LC84-15.pdf
(46 pages)
Specifications of EPM9320LC84-15
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
20
Number Of Macrocells
320
Number Of Gates
6000
Number Of I /o
60
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
84-PLCC
Voltage
3.3V/5V
Memory Type
EEPROM
Number Of Logic Elements/cells
20
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2362-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM9320LC84-15
Manufacturer:
ALTERA
Quantity:
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Part Number:
EPM9320LC84-15
Manufacturer:
ALTERA20
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Company:
Part Number:
EPM9320LC84-15N
Manufacturer:
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Quantity:
4
Altera Corporation
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 9000 Device
The time required to program a single MAX 9000 device in-system can be
calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 9000 device
can be calculated from the following formula:
where: t
t
t
PR OG
VER
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t
PROG
PPULSE
VER
VPULSE
PP ULSE
PTCK
VTCK
+
+
C ycle
--------------------------------
MAX 9000 Programmable Logic Device Family Data Sheet
Cyc le
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
TC K
f
T CK
VTC K
verify the EEPROM cells
PTC K
21