XC9536XL-5VQG44C Xilinx Inc, XC9536XL-5VQG44C Datasheet
XC9536XL-5VQG44C
Manufacturer Part Number
XC9536XL-5VQG44C
Description
IC CPLD 36 MCELL 3.3V 44-VQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr
Datasheet
1.XC9536XL-5VQG44C.pdf
(5 pages)
Specifications of XC9536XL-5VQG44C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
5.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
36
Number Of Gates
800
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.3V
Memory Type
FLASH
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Other names
122-1465
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
k
DS108-1 (v1.7) April 3, 2007
Features
•
•
•
•
•
•
•
•
•
Table 1: XA9500XL Device Family
DS108-1 (v1.7) April 3, 2007
Product Specification
XA9536XL
XA9572XL
XA95144XL
© 2002-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
AEC-Q100 device qualification and full PPAP support
available in both extended temperature Q-grade and
I-grade.
Guaranteed to meet full electrical specifications over
T
(Q-grade)
System frequency up to 64.5 MHz (15.5 ns)
Available in small footprint packages
Optimized for high-performance 3.3V systems
-
-
Advanced system features
-
-
-
-
-
Slew rate control on individual outputs for reducing EMI
generation
Refer to XC9500XL Family data sheet (DS054) for
architecture description
Refer to XA9536XL data sheet (DS598), the
XA9572XL data sheet (DS599), and the XA95144XL
data sheet (DS600) for pin tables
A
Device
= -40° C to +105° C with T
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals — ideal for multi-voltage system interfacing
and level shifting
Technology: 0.35 μm CMOS process
In-system programmable enabling higher system
reliability through reduced handling and reducing
production programming times
Superior pin-locking and routability with
FastCONNECT™ II switch matrix allowing for
multiple design iterations without board re-spins
Input hysteresis on all user and boundary-scan pin
inputs to reduce noise on input signals
Bus-hold circuitry on all user pin inputs which
reduces cost associated with pull-up resistors and
reduces bus loading
Full IEEE Standard 1149.1 boundary-scan (JTAG)
for in-system device testing
·
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Fast concurrent programming
Temperature Grade
R
I, Q
I, Q
I
J
Maximum = +125° C
Macrocells
144
36
72
0
0
www.xilinx.com
0
XA9500XL Automotive CPLD
Product Family
Product Specification
•
WARNING: Programming temperature range of
T
Description
The XA9500XL 3.3V CPLD Automotive XA product family is
targeted for leading-edge, high-performance automotive
applications that require either automotive industrial (–40°C
to +85°C ambient) or extended (–40°C to +105°C ambient)
temperature reconfigurable devices.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. Each macrocell in an XA9500XL automotive device
must be configured for low-power mode (default mode for
XA9500XL devices). In addition, unused product-terms and
macrocells are automatically deactivated by the software to
further conserve power.
For a general estimate of I
used:
I
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
with the design application and should be verified during
CC
A
Usable Gates
= 0° C to +70° C
(mA) = MC(0.052*PT + 0.272) + 0.04 * MC
Xilinx received ISO/TS 16949 Certification in March
2005.
where:
MC = # macrocells
PT = average number of product terms per macrocell
f = maximum clock frequency
MC
(~12%)
1,600
3,200
800
TOG
= average % of flip-flops toggling per clock
Registers
CC
144
36
72
, the following equation may be
f
SYSTEM
CC
TOG
64.5
64.5
64.5
value varies
*MC* f
(MHz)
1
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XC9536XL-5VQG44C Summary of contents
Page 1
R DS108-1 (v1.7) April 3, 2007 Features • AEC-Q100 device qualification and full PPAP support available in both extended temperature Q-grade and I-grade. • Guaranteed to meet full electrical specifications over T = -40° +105° C with ...
Page 2
XA9500XL Automotive CPLD Product Family Table 2: XA9500XL Packages and User I/O Pins (not including four dedicated JTAG pins) Device VQG44 XA9536XL 34 XA9572XL 34 XA95144XL -- Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input ...
Page 3
R Component Availability Pins Type Code -15 XA9536XL XA9572XL -15 XA95144XL -15 Notes Automotive Extended Temperature ( Automotive Industrial Temperature (T 3. All packages Pb-free. Ordering Information Example: Device Type Speed Grade Device Ordering ...
Page 4
XA9500XL Automotive CPLD Product Family 7. Do not drive I/Os pins above the V I/O bank. a. The current flow can go into V voltage regulator can also increase undesired leakage current associated with the device ...
Page 5
... The following table shows the revision history for this document. Date Version 05/17/02 1.0 Initial Xilinx release. 07/17/02 1.1 Updated N 02/03/03 1.2 Added reference to XC9500XL, XC9536XL, and XC9572XL data sheets. 05/21/04 1.3 Updated the VQ44 column of 10/18/04 1.4 Extensive edits to update family from IQ to XA. 09/29/05 1.5 Changes to packaging information. 01/12/07 1 ...