XC9572XL-10VQG44C Xilinx Inc, XC9572XL-10VQG44C Datasheet - Page 15
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XC9572XL-10VQG44C
Manufacturer Part Number
XC9572XL-10VQG44C
Description
IC CPLD 72MCRCELL 10NS 44VQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr
Specifications of XC9572XL-10VQG44C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
72
Number Of Gates
1600
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.3V
Memory Type
FLASH
Cpld Type
FLASH
No. Of Macrocells
72
No. Of I/o's
34
Propagation Delay
10ns
Global Clock Setup Time
6.5ns
Frequency
100MHz
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1512 - KIT DESIGN CPLD W/BATT HOLDER
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1448
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC9572XL-10VQG44C
Manufacturer:
XILINX
Quantity:
2 720
Company:
Part Number:
XC9572XL-10VQG44C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC9572XL-10VQG44C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC9572XL-10VQG44C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Detailed timing information may be derived from the full tim-
ing model shown in
DS054 (v2.5) May 22, 2009
Product Specification
T
PSU
R
Setup Time = T
T
T
T
Propagation Delay = T
T
GCK
GSR
GTS
IN
Figure
Combinatorial
P-Term Clock
Combinatorial
Logic
Logic
Path
(a)
16. The values and explanations
PSU
(c)
T
T
T
T
T
LOGILP
PD
Clock to Out Time = T
PTCK
PTSR
PTTS
LOGI
D/T Q
Figure 16: Detailed Timing Model
Figure 15: Basic Timing Model
S*T
T
PTA
www.xilinx.com
PCO
PCO
D/T
CE
for each parameter are given in the individual device data
sheets.
XC9500XL High-Performance CPLD Family Data Sheet
T
T
SUI
HI
T
T
T
SR
T
PDI
AOI
RAI
F
T
Macrocell
COI
Q
Setup Time = T
Internal System Cycle Time = T
Combinatorial
Combinatorial
Logic
Logic
T
SU
OUT
(b)
(d)
Clock to Out Time = T
D/T Q
T
D/T Q
SLEW
SYSTEM
DS054_15_042101
DS054_16_042101
T
CO
T
EN
CO
15