ATF1502BE-7AU44 Atmel, ATF1502BE-7AU44 Datasheet - Page 3
![IC CPLD EE HP 7NS 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATF1502BE-7AU44
Manufacturer Part Number
ATF1502BE-7AU44
Description
IC CPLD EE HP 7NS 44TQFP
Manufacturer
Atmel
Series
ATF1502BEr
Datasheet
1.ATF1502BE-7AU44.pdf
(24 pages)
Specifications of ATF1502BE-7AU44
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Macrocells
32
Number Of I /o
32
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Features
CMOS/TTL Compatible
Voltage
1.8V
Memory Type
EEPROM
For Use With
ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATF1502BE-7AU44
Manufacturer:
AD
Quantity:
92
Figure 1-2.
3492A–PLD–12/05
Block Diagram
32
Each of the 32 macrocells generates a buried feedback signal that goes to the global bus (see
Figure
block then selects 40 individual signals from the global bus. Each macrocell also generates a
foldback logic term that goes to a regional bus. Cascade logic between macrocells in the
ATF1502BE allows fast, efficient generation of complex logic functions. The ATF1502BE con-
tains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40
product terms.
The ATF1502BE macrocell, shown in
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
A security fuse, when programmed, protects the contents of the ATF1502BE. Two bytes
(16 bits) of User Signature are accessible to the user for purposes such as storing project name,
part number, revision or date. The User Signature is accessible regardless of the state of the
security fuse.
The ATF1502BE device is an In-System Programming (ISP) device. It uses the industry-stan-
dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan
Description Language (BSDL). ISP allows the device to be programmed without removing it from
the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design
modifications to be made in the field via software.
1-2). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
Figure
1-3, is flexible enough to support highly complex
B
ATF1502BE
3