ATF1502BE-7AU44 Atmel, ATF1502BE-7AU44 Datasheet - Page 7
![IC CPLD EE HP 7NS 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATF1502BE-7AU44
Manufacturer Part Number
ATF1502BE-7AU44
Description
IC CPLD EE HP 7NS 44TQFP
Manufacturer
Atmel
Series
ATF1502BEr
Datasheet
1.ATF1502BE-7AU44.pdf
(24 pages)
Specifications of ATF1502BE-7AU44
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Macrocells
32
Number Of I /o
32
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Features
CMOS/TTL Compatible
Voltage
1.8V
Memory Type
EEPROM
For Use With
ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATF1502BE-7AU44
Manufacturer:
AD
Quantity:
92
2.1
3. Speed/Power Management
3.1
4. Security Feature
3492A–PLD–12/05
Schmitt Trigger
Output Drive Capability
The Input Buffer of each input and I/O pin has an optional schmitt trigger setting. The schmitt
trigger option can be used to buffer inputs with slow rise times.
Unlike conventional CPLDs with sense amplifiers, the ATF1502BE is designed using low-power
full CMOS design techniques. This enables the ATF1502BE to achieve extremely low power
consumption over the full operating frequency spectrum.
The ATF1502BE also has an optional power-down mode. In this mode, current drops to below
100 µA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used
to power down the part. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any
enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s mac-
rocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins.
Each output has a high/low drive option. The low drive option (slow slew rate) can be used to
reduce system noise by slowing down outputs that do not need to operate at maximum speed or
drive strength. Outputs default to high drive strength by Atmel software and can be set to low
drive strength through the slew rate option.
A fuse is provided to prevent unauthorized copying of the ATF1502BE fuse patterns. Once pro-
grammed, fuse verify is inhibited. However, the 16-bit User Signature remains accessible. To
reset this feature, the entire memory array in the device must be erased.
ATF1502BE
7