EPM7064AETI44-7N Altera, EPM7064AETI44-7N Datasheet - Page 54
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EPM7064AETI44-7N
Manufacturer Part Number
EPM7064AETI44-7N
Description
IC MAX 7000 CPLD 64 44-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7064AETI44-7N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Cpld Type
EEPROM
No. Of Macrocells
64
No. Of I/o's
36
Propagation Delay
7.5ns
Global Clock Setup Time
4.7ns
Frequency
135.1MHz
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2011
EPM7064AETI44-7N
EPM7064AETI44-7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7064AETI44-7N
Manufacturer:
ALTERA
Quantity:
20
Company:
Part Number:
EPM7064AETI44-7N
Manufacturer:
ALTERA
Quantity:
37
MAX 7000A Programmable Logic Device Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
Power
Consumption
54
t
t
t
t
t
t
t
t
Symbol
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 30. EPM7256A Internal Timing Parameters (Part 2 of 2)
These values are specified under the recommended operating conditions shown in
Figure 12
These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
This minimum pulse width for preset and clear applies for both global clear and array controls. The t
must be added to this minimum width if the clear or reset signal incorporates the t
path.
This parameter is measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
Operating conditions: V
The t
running in low-power mode.
LPA
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
parameter must be added to the t
for more information on switching waveforms.
Parameter
CCIO
Supply power (P) versus frequency (f
devices is calculated with the following equation:
P = P
The P
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices).
The I
logic. The I
I
(A × MC
CCINT
= 2.5 ± 0.2 V for commercial and industrial use.
CCINT
INT
IO
(2)
(6)
Conditions
=
value, which depends on the device output load characteristics
TON
+ P
CCINT
value depends on the switching frequency and the application
IO
) + [B × (MC
LAD
= I
, t
value is calculated with the following equation:
CCINT
LAC
Min
, t
IC
-6
, t
× V
DEV
Max
11.0
EN
1.6
2.7
2.5
1.1
2.3
2.3
1.3
CC
, t
SEXP
– MC
+ P
Min
, t
IO
ACL
TON
-7
Note (1)
Speed Grade
Max
10.0
MAX
, and t
2.0
3.4
3.1
1.4
2.9
2.9
1.6
)] + (C × MC
, in MHz) for MAX 7000A
CPPW
Min
LAD
Table 14 on page
-10
parameters for macrocells
Max
10.0
parameter into the signal
2.7
4.5
4.2
1.8
3.8
3.8
2.1
USED
Altera Corporation
Min
× f
MAX
-12
LPA
28. See
Max
10.0
3.2
5.4
5.0
2.2
4.6
4.6
2.6
parameter
× tog
Unit
ns
ns
ns
ns
ns
ns
ns
ns
LC
)