EPM7256AEQC208-10 Altera, EPM7256AEQC208-10 Datasheet - Page 18
![IC MAX 7000 CPLD 256 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EPM7256AEQC208-10
Manufacturer Part Number
EPM7256AEQC208-10
Description
IC MAX 7000 CPLD 256 208-PQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7256AEQC208-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2349
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7256AEQC208-10
Manufacturer:
ALTERA
Quantity:
12 388
Part Number:
EPM7256AEQC208-10
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM7256AEQC208-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
18
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000A Device
The time required to program a single MAX 7000A device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 7000A device
can be calculated from the following formula:
where: t
t
t
PROG
VER
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t
PROG
PPULSE
VER
VPULSE
PPULSE
PTCK
VTCK
+
+
Cycle VTCK
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f TCK
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
f
TCK
verify the EEPROM cells
PTCK
Altera Corporation