EPM7256AEQC208-10 Altera, EPM7256AEQC208-10 Datasheet - Page 32
![IC MAX 7000 CPLD 256 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EPM7256AEQC208-10
Manufacturer Part Number
EPM7256AEQC208-10
Description
IC MAX 7000 CPLD 256 208-PQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7256AEQC208-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2349
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7256AEQC208-10
Manufacturer:
ALTERA
Quantity:
12 388
Part Number:
EPM7256AEQC208-10
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM7256AEQC208-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
Figure 11. MAX 7000A Timing Model
32
Delay
f
Input
t
I N
Delay
PIA
t
PIA
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters.
between internal and external delay parameters.
See
information.
Application Note 94 (Understanding MAX 7000 Timing)
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
Delay
t
t
t
t
t
t
t
GLOB
SEXP
LAD
LAC
I C
EN
IOE
Expander Delay
Parallel
t
PEXP
Figure 12
Input Delay
Fast
t
F I N
Register
t
t
t
t
t
t
t
t
shows the timing relationship
Delay
SU
H
PRE
CLR
RD
COMB
FSU
FH
Altera Corporation
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
X1
for more
Delay
I/O
t
I O